Preparation method of floating gate
The invention provides a preparation method of a floating gate, which comprises the following steps of: providing a substrate, forming a silicon nitride layer to cover the substrate, etching the silicon nitride layer to form a plurality of silicon nitride patterns, enabling the side walls of the sil...
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| creator | WANG DUNNIAN XIE RONGYUAN ZHU JINZHUAN ZHANG XINGCHI LIN TAOTIAN |
| description | The invention provides a preparation method of a floating gate, which comprises the following steps of: providing a substrate, forming a silicon nitride layer to cover the substrate, etching the silicon nitride layer to form a plurality of silicon nitride patterns, enabling the side walls of the silicon nitride patterns to be vertical due to the characteristics of a silicon nitride material, and exposing a part of the substrate between two adjacent silicon nitride patterns; forming a floating gate material layer to cover the silicon nitride patterns and filling the floating gate material layer on the substrate exposed between two adjacent silicon nitride patterns; etching to remove the floating gate material layer above the silicon nitride pattern and partial thickness of the silicon nitride pattern, taking the reserved floating gate material layer as a floating gate, and enabling the lower part side wall of the floating gate to be in contact with the side wall of the silicon nitride pattern so that the lower |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN118398484A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN118398484A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN118398484A3</originalsourceid><addsrcrecordid>eNrjZFAOKEotSCxKLMnMz1PITS3JyE9RyE9TSMvJBwrlpSukJ5ak8jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeGc_Q0MLY0sLEwsTR2Ni1AAA4cImdg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Preparation method of floating gate</title><source>esp@cenet</source><creator>WANG DUNNIAN ; XIE RONGYUAN ; ZHU JINZHUAN ; ZHANG XINGCHI ; LIN TAOTIAN</creator><creatorcontrib>WANG DUNNIAN ; XIE RONGYUAN ; ZHU JINZHUAN ; ZHANG XINGCHI ; LIN TAOTIAN</creatorcontrib><description>The invention provides a preparation method of a floating gate, which comprises the following steps of: providing a substrate, forming a silicon nitride layer to cover the substrate, etching the silicon nitride layer to form a plurality of silicon nitride patterns, enabling the side walls of the silicon nitride patterns to be vertical due to the characteristics of a silicon nitride material, and exposing a part of the substrate between two adjacent silicon nitride patterns; forming a floating gate material layer to cover the silicon nitride patterns and filling the floating gate material layer on the substrate exposed between two adjacent silicon nitride patterns; etching to remove the floating gate material layer above the silicon nitride pattern and partial thickness of the silicon nitride pattern, taking the reserved floating gate material layer as a floating gate, and enabling the lower part side wall of the floating gate to be in contact with the side wall of the silicon nitride pattern so that the lower</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240726&DB=EPODOC&CC=CN&NR=118398484A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240726&DB=EPODOC&CC=CN&NR=118398484A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WANG DUNNIAN</creatorcontrib><creatorcontrib>XIE RONGYUAN</creatorcontrib><creatorcontrib>ZHU JINZHUAN</creatorcontrib><creatorcontrib>ZHANG XINGCHI</creatorcontrib><creatorcontrib>LIN TAOTIAN</creatorcontrib><title>Preparation method of floating gate</title><description>The invention provides a preparation method of a floating gate, which comprises the following steps of: providing a substrate, forming a silicon nitride layer to cover the substrate, etching the silicon nitride layer to form a plurality of silicon nitride patterns, enabling the side walls of the silicon nitride patterns to be vertical due to the characteristics of a silicon nitride material, and exposing a part of the substrate between two adjacent silicon nitride patterns; forming a floating gate material layer to cover the silicon nitride patterns and filling the floating gate material layer on the substrate exposed between two adjacent silicon nitride patterns; etching to remove the floating gate material layer above the silicon nitride pattern and partial thickness of the silicon nitride pattern, taking the reserved floating gate material layer as a floating gate, and enabling the lower part side wall of the floating gate to be in contact with the side wall of the silicon nitride pattern so that the lower</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAOKEotSCxKLMnMz1PITS3JyE9RyE9TSMvJBwrlpSukJ5ak8jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeGc_Q0MLY0sLEwsTR2Ni1AAA4cImdg</recordid><startdate>20240726</startdate><enddate>20240726</enddate><creator>WANG DUNNIAN</creator><creator>XIE RONGYUAN</creator><creator>ZHU JINZHUAN</creator><creator>ZHANG XINGCHI</creator><creator>LIN TAOTIAN</creator><scope>EVB</scope></search><sort><creationdate>20240726</creationdate><title>Preparation method of floating gate</title><author>WANG DUNNIAN ; XIE RONGYUAN ; ZHU JINZHUAN ; ZHANG XINGCHI ; LIN TAOTIAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118398484A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>WANG DUNNIAN</creatorcontrib><creatorcontrib>XIE RONGYUAN</creatorcontrib><creatorcontrib>ZHU JINZHUAN</creatorcontrib><creatorcontrib>ZHANG XINGCHI</creatorcontrib><creatorcontrib>LIN TAOTIAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WANG DUNNIAN</au><au>XIE RONGYUAN</au><au>ZHU JINZHUAN</au><au>ZHANG XINGCHI</au><au>LIN TAOTIAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Preparation method of floating gate</title><date>2024-07-26</date><risdate>2024</risdate><abstract>The invention provides a preparation method of a floating gate, which comprises the following steps of: providing a substrate, forming a silicon nitride layer to cover the substrate, etching the silicon nitride layer to form a plurality of silicon nitride patterns, enabling the side walls of the silicon nitride patterns to be vertical due to the characteristics of a silicon nitride material, and exposing a part of the substrate between two adjacent silicon nitride patterns; forming a floating gate material layer to cover the silicon nitride patterns and filling the floating gate material layer on the substrate exposed between two adjacent silicon nitride patterns; etching to remove the floating gate material layer above the silicon nitride pattern and partial thickness of the silicon nitride pattern, taking the reserved floating gate material layer as a floating gate, and enabling the lower part side wall of the floating gate to be in contact with the side wall of the silicon nitride pattern so that the lower</abstract><oa>free_for_read</oa></addata></record> |
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| title | Preparation method of floating gate |
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