Mainboard time sequence control circuit
The invention relates to a mainboard time sequence control circuit, and belongs to the technical field of computers. The mainboard time sequence control circuit comprises a + 12V input slow start circuit, a hot plug control circuit and a module power supply cascade control circuit, and the module po...
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| creator | ZHAO BOYING SHI MEILIN GOU XIANGYANG ZHU YINGBO WANG XIANG NING CHUNSHENG WANG WENJUAN |
| description | The invention relates to a mainboard time sequence control circuit, and belongs to the technical field of computers. The mainboard time sequence control circuit comprises a + 12V input slow start circuit, a hot plug control circuit and a module power supply cascade control circuit, and the module power supply cascade control circuit comprises a S5 domain power supply control circuit, an S3 domain power supply control circuit and an S0 domain power supply control circuit. According to the mainboard time sequence control circuit built by the hardware, the CPLD function is replaced by the mainboard time sequence control circuit built by the hardware, and the mainboard time sequence control circuit built by the hardware has the advantages that the overall power consumption and the design cost of the mainboard are reduced, the fault risk is reduced, meanwhile, the occupied area of a board card is reduced, and the use flexibility of components is improved.
本发明涉及一种主板时序控制电路，属于计算机技术领域。本发明的主板时序控制电路包括：+12V输入缓起电路、热插拔控制电路 |
| format | Patent |
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本发明涉及一种主板时序控制电路，属于计算机技术领域。本发明的主板时序控制电路包括：+12V输入缓起电路、热插拔控制电路</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240621&DB=EPODOC&CC=CN&NR=118226943A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240621&DB=EPODOC&CC=CN&NR=118226943A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZHAO BOYING</creatorcontrib><creatorcontrib>SHI MEILIN</creatorcontrib><creatorcontrib>GOU XIANGYANG</creatorcontrib><creatorcontrib>ZHU YINGBO</creatorcontrib><creatorcontrib>WANG XIANG</creatorcontrib><creatorcontrib>NING CHUNSHENG</creatorcontrib><creatorcontrib>WANG WENJUAN</creatorcontrib><title>Mainboard time sequence control circuit</title><description>The invention relates to a mainboard time sequence control circuit, and belongs to the technical field of computers. The mainboard time sequence control circuit comprises a + 12V input slow start circuit, a hot plug control circuit and a module power supply cascade control circuit, and the module power supply cascade control circuit comprises a S5 domain power supply control circuit, an S3 domain power supply control circuit and an S0 domain power supply control circuit. According to the mainboard time sequence control circuit built by the hardware, the CPLD function is replaced by the mainboard time sequence control circuit built by the hardware, and the mainboard time sequence control circuit built by the hardware has the advantages that the overall power consumption and the design cost of the mainboard are reduced, the fault risk is reduced, meanwhile, the occupied area of a board card is reduced, and the use flexibility of components is improved.
本发明涉及一种主板时序控制电路，属于计算机技术领域。本发明的主板时序控制电路包括：+12V输入缓起电路、热插拔控制电路</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD3TczMS8pPLEpRKMnMTVUoTi0sTc1LTlVIzs8rKcrPUUjOLEouzSzhYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GhhZGRmaWJsaOxsSoAQCwQCgf</recordid><startdate>20240621</startdate><enddate>20240621</enddate><creator>ZHAO BOYING</creator><creator>SHI MEILIN</creator><creator>GOU XIANGYANG</creator><creator>ZHU YINGBO</creator><creator>WANG XIANG</creator><creator>NING CHUNSHENG</creator><creator>WANG WENJUAN</creator><scope>EVB</scope></search><sort><creationdate>20240621</creationdate><title>Mainboard time sequence control circuit</title><author>ZHAO BOYING ; SHI MEILIN ; GOU XIANGYANG ; ZHU YINGBO ; WANG XIANG ; NING CHUNSHENG ; WANG WENJUAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118226943A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>ZHAO BOYING</creatorcontrib><creatorcontrib>SHI MEILIN</creatorcontrib><creatorcontrib>GOU XIANGYANG</creatorcontrib><creatorcontrib>ZHU YINGBO</creatorcontrib><creatorcontrib>WANG XIANG</creatorcontrib><creatorcontrib>NING CHUNSHENG</creatorcontrib><creatorcontrib>WANG WENJUAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZHAO BOYING</au><au>SHI MEILIN</au><au>GOU XIANGYANG</au><au>ZHU YINGBO</au><au>WANG XIANG</au><au>NING CHUNSHENG</au><au>WANG WENJUAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Mainboard time sequence control circuit</title><date>2024-06-21</date><risdate>2024</risdate><abstract>The invention relates to a mainboard time sequence control circuit, and belongs to the technical field of computers. The mainboard time sequence control circuit comprises a + 12V input slow start circuit, a hot plug control circuit and a module power supply cascade control circuit, and the module power supply cascade control circuit comprises a S5 domain power supply control circuit, an S3 domain power supply control circuit and an S0 domain power supply control circuit. According to the mainboard time sequence control circuit built by the hardware, the CPLD function is replaced by the mainboard time sequence control circuit built by the hardware, and the mainboard time sequence control circuit built by the hardware has the advantages that the overall power consumption and the design cost of the mainboard are reduced, the fault risk is reduced, meanwhile, the occupied area of a board card is reduced, and the use flexibility of components is improved.
本发明涉及一种主板时序控制电路，属于计算机技术领域。本发明的主板时序控制电路包括：+12V输入缓起电路、热插拔控制电路</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Mainboard time sequence control circuit |
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