Method for reducing expansion and shrinkage difference of base material for manufacturing multi-layer printed circuit board

The invention belongs to the technical field of circuit boards, and particularly relates to a method for reducing the expansion and shrinkage difference of a multi-layer printed circuit board manufacturing base material, a plurality of core layers and a press-fit heat conduction layer are included,...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: WU BOPING, SHEN JIAXIAO, HUANG SHIYU, LI JIUJUAN, YANG WENJUN, WANG SHOUXU, TANG HUIRONG, ZHOU GUOYUN
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator WU BOPING
SHEN JIAXIAO
HUANG SHIYU
LI JIUJUAN
YANG WENJUN
WANG SHOUXU
TANG HUIRONG
ZHOU GUOYUN
description The invention belongs to the technical field of circuit boards, and particularly relates to a method for reducing the expansion and shrinkage difference of a multi-layer printed circuit board manufacturing base material, a plurality of core layers and a press-fit heat conduction layer are included, each core layer comprises a base material and substrates arranged on the two sides of the base material, the core layers are used for circuit manufacturing and detection, and the press-fit heat conduction layer is arranged on the base material. The press-fit heat conduction layer comprises a second polypropylene layer and a press-fit copper foil layer; comprising the following steps that S1, a first polypropylene layer is arranged between every two adjacent core layers, and second polypropylene layers are arranged on the two sides of the outermost core layer; s2, arranging a laminated copper foil layer on the outer side of the second polypropylene layer to obtain a laminated plate; and S3, the laminated plate is pl
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN118158925A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN118158925A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN118158925A3</originalsourceid><addsrcrecordid>eNqNjEsKwjAQQLtxIeodxgN0UaVQl1IUN7pyX6bJpA2mkzBJQPHyfvAArh48Hm9ePM-URq_BeAEhnZXlAegekKP1DMga4iiWbzgQaGsMCbEi8AZ6jAQTJhKL7juYkLNBlbJ8LlN2yZYOHyQQ3iaRBmVFZZug9yh6WcwMukirHxfF-ni4tqeSgu8oBlTElLr2UlVNVTe7Tb3f_tO8AOgdR_o</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for reducing expansion and shrinkage difference of base material for manufacturing multi-layer printed circuit board</title><source>esp@cenet</source><creator>WU BOPING ; SHEN JIAXIAO ; HUANG SHIYU ; LI JIUJUAN ; YANG WENJUN ; WANG SHOUXU ; TANG HUIRONG ; ZHOU GUOYUN</creator><creatorcontrib>WU BOPING ; SHEN JIAXIAO ; HUANG SHIYU ; LI JIUJUAN ; YANG WENJUN ; WANG SHOUXU ; TANG HUIRONG ; ZHOU GUOYUN</creatorcontrib><description>The invention belongs to the technical field of circuit boards, and particularly relates to a method for reducing the expansion and shrinkage difference of a multi-layer printed circuit board manufacturing base material, a plurality of core layers and a press-fit heat conduction layer are included, each core layer comprises a base material and substrates arranged on the two sides of the base material, the core layers are used for circuit manufacturing and detection, and the press-fit heat conduction layer is arranged on the base material. The press-fit heat conduction layer comprises a second polypropylene layer and a press-fit copper foil layer; comprising the following steps that S1, a first polypropylene layer is arranged between every two adjacent core layers, and second polypropylene layers are arranged on the two sides of the outermost core layer; s2, arranging a laminated copper foil layer on the outer side of the second polypropylene layer to obtain a laminated plate; and S3, the laminated plate is pl</description><language>chi ; eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240607&amp;DB=EPODOC&amp;CC=CN&amp;NR=118158925A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240607&amp;DB=EPODOC&amp;CC=CN&amp;NR=118158925A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WU BOPING</creatorcontrib><creatorcontrib>SHEN JIAXIAO</creatorcontrib><creatorcontrib>HUANG SHIYU</creatorcontrib><creatorcontrib>LI JIUJUAN</creatorcontrib><creatorcontrib>YANG WENJUN</creatorcontrib><creatorcontrib>WANG SHOUXU</creatorcontrib><creatorcontrib>TANG HUIRONG</creatorcontrib><creatorcontrib>ZHOU GUOYUN</creatorcontrib><title>Method for reducing expansion and shrinkage difference of base material for manufacturing multi-layer printed circuit board</title><description>The invention belongs to the technical field of circuit boards, and particularly relates to a method for reducing the expansion and shrinkage difference of a multi-layer printed circuit board manufacturing base material, a plurality of core layers and a press-fit heat conduction layer are included, each core layer comprises a base material and substrates arranged on the two sides of the base material, the core layers are used for circuit manufacturing and detection, and the press-fit heat conduction layer is arranged on the base material. The press-fit heat conduction layer comprises a second polypropylene layer and a press-fit copper foil layer; comprising the following steps that S1, a first polypropylene layer is arranged between every two adjacent core layers, and second polypropylene layers are arranged on the two sides of the outermost core layer; s2, arranging a laminated copper foil layer on the outer side of the second polypropylene layer to obtain a laminated plate; and S3, the laminated plate is pl</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjEsKwjAQQLtxIeodxgN0UaVQl1IUN7pyX6bJpA2mkzBJQPHyfvAArh48Hm9ePM-URq_BeAEhnZXlAegekKP1DMga4iiWbzgQaGsMCbEi8AZ6jAQTJhKL7juYkLNBlbJ8LlN2yZYOHyQQ3iaRBmVFZZug9yh6WcwMukirHxfF-ni4tqeSgu8oBlTElLr2UlVNVTe7Tb3f_tO8AOgdR_o</recordid><startdate>20240607</startdate><enddate>20240607</enddate><creator>WU BOPING</creator><creator>SHEN JIAXIAO</creator><creator>HUANG SHIYU</creator><creator>LI JIUJUAN</creator><creator>YANG WENJUN</creator><creator>WANG SHOUXU</creator><creator>TANG HUIRONG</creator><creator>ZHOU GUOYUN</creator><scope>EVB</scope></search><sort><creationdate>20240607</creationdate><title>Method for reducing expansion and shrinkage difference of base material for manufacturing multi-layer printed circuit board</title><author>WU BOPING ; SHEN JIAXIAO ; HUANG SHIYU ; LI JIUJUAN ; YANG WENJUN ; WANG SHOUXU ; TANG HUIRONG ; ZHOU GUOYUN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118158925A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>WU BOPING</creatorcontrib><creatorcontrib>SHEN JIAXIAO</creatorcontrib><creatorcontrib>HUANG SHIYU</creatorcontrib><creatorcontrib>LI JIUJUAN</creatorcontrib><creatorcontrib>YANG WENJUN</creatorcontrib><creatorcontrib>WANG SHOUXU</creatorcontrib><creatorcontrib>TANG HUIRONG</creatorcontrib><creatorcontrib>ZHOU GUOYUN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WU BOPING</au><au>SHEN JIAXIAO</au><au>HUANG SHIYU</au><au>LI JIUJUAN</au><au>YANG WENJUN</au><au>WANG SHOUXU</au><au>TANG HUIRONG</au><au>ZHOU GUOYUN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for reducing expansion and shrinkage difference of base material for manufacturing multi-layer printed circuit board</title><date>2024-06-07</date><risdate>2024</risdate><abstract>The invention belongs to the technical field of circuit boards, and particularly relates to a method for reducing the expansion and shrinkage difference of a multi-layer printed circuit board manufacturing base material, a plurality of core layers and a press-fit heat conduction layer are included, each core layer comprises a base material and substrates arranged on the two sides of the base material, the core layers are used for circuit manufacturing and detection, and the press-fit heat conduction layer is arranged on the base material. The press-fit heat conduction layer comprises a second polypropylene layer and a press-fit copper foil layer; comprising the following steps that S1, a first polypropylene layer is arranged between every two adjacent core layers, and second polypropylene layers are arranged on the two sides of the outermost core layer; s2, arranging a laminated copper foil layer on the outer side of the second polypropylene layer to obtain a laminated plate; and S3, the laminated plate is pl</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN118158925A
source esp@cenet
subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title Method for reducing expansion and shrinkage difference of base material for manufacturing multi-layer printed circuit board
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T16%3A49%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WU%20BOPING&rft.date=2024-06-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN118158925A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true