Three-transistor embedded dynamic random access memory gain cell

The invention relates to a three-transistor embedded dynamic random access memory gain cell. Embodiments herein relate to a three-transistor gain cell that is provided with a complementary field effect transistor device to achieve scaling. The cell includes an n-type layer disposed over a p-type layer. In one implementation, two nMOS transistors are arranged over one pMOS transistor, and a conduction path is provided to connect a gate of one of the nMOS transistors to a storage node in a p-type layer, where the storage node is coupled to a drain of the pMOS transistor. In another implementation, one nMOS transistor is disposed over two pMOS transistors, and a conduction path is provided to connect a gate of one of the pMOS transistors to a storage node in the n-type layer, where the storage node is coupled to a source of the nMOS transistor. 本申请涉及三晶体管嵌入式动态随机访问存储器增益单元。本文的实施例涉及三晶体管增益单元，该三晶体管增益单元被利用互补场效应晶体管器件来提供以实现缩放。该单元包括布置在p型层上方的n型层。在一种实现方式中，两个nMOS晶体管被布置在一个pMOS晶体管上方，并且提供了传导路径来将nMOS晶体管之一的栅极连接到p型层中的存储节点，其中存储节点耦合