Layout pattern of static random access memory and forming method thereof

A layout pattern of a static random access memory (SRAM) includes at least a plurality of gate structures on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors including: two pull-up transistors (PUs) and two pull-down transistors (PDs) together forming a latch, and two access transistors (PGs) connected to the latch circuit, and in any one of the static random access memory cells, one of the PGs is connected to the latch circuit. The fin-shaped structure included in the pull-up transistor (PU) is defined as a pull-up transistor fin-shaped structure, the fin-shaped structure included in the pull-down transistor (PD) is defined as a pull-down transistor fin-shaped structure, and the fin-shaped structure included in the access transistor (PG) is defined as an access transistor fin-shaped structure. Wherein a width of the pull-down transistor fin structure is wider than a width of the access transistor fin structu