Distributed system-level cache

The invention relates to a distributed system level cache. A processor and a method of obtaining data for a processor are provided. The processor includes at least a first core, a second core, and a distributed cache. The distributed cache includes a first cache slice connected to the first core and a second cache slice connected to the second core and the first cache slice. The first cache slice is configured to receive a memory access request from the first core and forward the memory access request to the second cache slice. 本发明涉及分布式系统级高速缓存。提供了一种处理器和一种为处理器获得数据的方法。所述处理器包括至少第一核、第二核和分布式高速缓存。所述分布式高速缓存包括连接到所述第一核的第一高速缓存切片以及连接到所述第二核和所述第一高速缓存切片的第二高速缓存切片。所述第一高速缓存切片被配置成从所述第一核接收存储器访问请求，并将所述存储器访问请求转发到所述第二高速缓存切片。