Chip hardware synthesis method based on multi-layer intermediate representation

The invention discloses a chip hardware synthesis method based on multi-layer intermediate representation, and the method comprises the steps: designing a multi-stage intermediate representation system Hector which employs intermediate representation IR of a high stage and a low stage, and the intermediate representation IR is a topological representation ToR IR and a hybrid elastic module HEC IR; the middle of the high layer of the Hector represents a ToR IR design time graph for representing operation scheduling; the time diagram is a state transition diagram which retains high-level control logic; the scheduling comprises static operation controlled by a state machine, assembly line operation and dynamic operation based on handshake signal control dependence; the middle of the bottom layer of the Hector represents HEC IR to carry out explicit instantiation on a hardware module, and operation is allocated to a specific calculation unit; the method comprises the following steps of: generating a synthesizable