Clock synchronization method, device, system and chip
The invention discloses a clock synchronization method, device, system and chip, and the method comprises the steps: receiving a second pulse signal and a clock synchronization protocol message, obtaining timestamp information through the analysis of the clock synchronization protocol message, carry...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses a clock synchronization method, device, system and chip, and the method comprises the steps: receiving a second pulse signal and a clock synchronization protocol message, obtaining timestamp information through the analysis of the clock synchronization protocol message, carrying out the frequency division of a first reference clock signal through a fractional frequency division phase-locked loop circuit, and obtaining a second reference clock signal; therefore, a plurality of first sub-clock signals are obtained. Sampling the second pulse signal by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals; taking a first jump edge of the first sampling signal as a sampling point, and determining a plurality of first sampling values of the plurality of first sampling signals at the sampling point; and realizing clock synchronization based on the timestamp information and the plurality of first sampling values. According to the invention, after freque |
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