Integrated memory array and peripheral metal silicide
Various applications can include an apparatus having a memory device with metal digital lines coupled to various digital line contacts of a memory array in an integration process of the metal lines with metal contacts of transistors in a periphery of a memory array region, wherein the metal silicide...
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creator | SRIVASTAVA SUDHIR BENSON RUSSELL A SINGANAMALLA RAGHUNATH |
description | Various applications can include an apparatus having a memory device with metal digital lines coupled to various digital line contacts of a memory array in an integration process of the metal lines with metal contacts of transistors in a periphery of a memory array region, wherein the metal silicide is formed on the grid electrode of the transistor. The metal silicide of each transistor can be coupled to the metal contact of the transistor. In the integration process, the material of the metal digital lines can be used as metal contacts to transistors in the periphery of the memory array region. In the integration process flow, the metal silicide can be formed by converting polysilicon formed on the memory array region and the periphery of the memory array region.
各种应用能包含设备,所述设备具有存储器装置,所述存储器装置具有金属数字线,其在金属线与存储器阵列区的外围中的晶体管的金属触点的集成工艺流程中耦合到存储器阵列的各种数字线触点,其中金属硅化物形成于晶体管的栅极上。每一晶体管的金属硅化物能耦合到所述晶体管的所述金属触点。在所述集成工艺流程中,所述金属数字线的材料能用作到存储器阵列区的外围中的晶体管的金属触点。在所述集成工艺流程中,能通过转换形成在所述存储器阵列区及所述存储器阵列区的所述外围上的多晶硅来形成所述金属硅化物。 |
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各种应用能包含设备,所述设备具有存储器装置,所述存储器装置具有金属数字线,其在金属线与存储器阵列区的外围中的晶体管的金属触点的集成工艺流程中耦合到存储器阵列的各种数字线触点,其中金属硅化物形成于晶体管的栅极上。每一晶体管的金属硅化物能耦合到所述晶体管的所述金属触点。在所述集成工艺流程中,所述金属数字线的材料能用作到存储器阵列区的外围中的晶体管的金属触点。在所述集成工艺流程中,能通过转换形成在所述存储器阵列区及所述存储器阵列区的所述外围上的多晶硅来形成所述金属硅化物。</description><language>chi ; eng</language><subject>ELECTRICITY</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240301&DB=EPODOC&CC=CN&NR=117641905A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240301&DB=EPODOC&CC=CN&NR=117641905A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SRIVASTAVA SUDHIR</creatorcontrib><creatorcontrib>BENSON RUSSELL A</creatorcontrib><creatorcontrib>SINGANAMALLA RAGHUNATH</creatorcontrib><title>Integrated memory array and peripheral metal silicide</title><description>Various applications can include an apparatus having a memory device with metal digital lines coupled to various digital line contacts of a memory array in an integration process of the metal lines with metal contacts of transistors in a periphery of a memory array region, wherein the metal silicide is formed on the grid electrode of the transistor. The metal silicide of each transistor can be coupled to the metal contact of the transistor. In the integration process, the material of the metal digital lines can be used as metal contacts to transistors in the periphery of the memory array region. In the integration process flow, the metal silicide can be formed by converting polysilicon formed on the memory array region and the periphery of the memory array region.
各种应用能包含设备,所述设备具有存储器装置,所述存储器装置具有金属数字线,其在金属线与存储器阵列区的外围中的晶体管的金属触点的集成工艺流程中耦合到存储器阵列的各种数字线触点,其中金属硅化物形成于晶体管的栅极上。每一晶体管的金属硅化物能耦合到所述晶体管的所述金属触点。在所述集成工艺流程中,所述金属数字线的材料能用作到存储器阵列区的外围中的晶体管的金属触点。在所述集成工艺流程中,能通过转换形成在所述存储器阵列区及所述存储器阵列区的所述外围上的多晶硅来形成所述金属硅化物。</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD1zCtJTS9KLElNUchNzc0vqlRILCpKBJJ5KQoFqUWZBRmpRYk5QLkSIFmcmZOZnJmSysPAmpaYU5zKC6W5GRTdXEOcPXRTC_LjU4sLEpNT81JL4p39DA3NzUwMLQ1MHY2JUQMAfEEtVw</recordid><startdate>20240301</startdate><enddate>20240301</enddate><creator>SRIVASTAVA SUDHIR</creator><creator>BENSON RUSSELL A</creator><creator>SINGANAMALLA RAGHUNATH</creator><scope>EVB</scope></search><sort><creationdate>20240301</creationdate><title>Integrated memory array and peripheral metal silicide</title><author>SRIVASTAVA SUDHIR ; BENSON RUSSELL A ; SINGANAMALLA RAGHUNATH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN117641905A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>SRIVASTAVA SUDHIR</creatorcontrib><creatorcontrib>BENSON RUSSELL A</creatorcontrib><creatorcontrib>SINGANAMALLA RAGHUNATH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SRIVASTAVA SUDHIR</au><au>BENSON RUSSELL A</au><au>SINGANAMALLA RAGHUNATH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated memory array and peripheral metal silicide</title><date>2024-03-01</date><risdate>2024</risdate><abstract>Various applications can include an apparatus having a memory device with metal digital lines coupled to various digital line contacts of a memory array in an integration process of the metal lines with metal contacts of transistors in a periphery of a memory array region, wherein the metal silicide is formed on the grid electrode of the transistor. The metal silicide of each transistor can be coupled to the metal contact of the transistor. In the integration process, the material of the metal digital lines can be used as metal contacts to transistors in the periphery of the memory array region. In the integration process flow, the metal silicide can be formed by converting polysilicon formed on the memory array region and the periphery of the memory array region.
各种应用能包含设备,所述设备具有存储器装置,所述存储器装置具有金属数字线,其在金属线与存储器阵列区的外围中的晶体管的金属触点的集成工艺流程中耦合到存储器阵列的各种数字线触点,其中金属硅化物形成于晶体管的栅极上。每一晶体管的金属硅化物能耦合到所述晶体管的所述金属触点。在所述集成工艺流程中,所述金属数字线的材料能用作到存储器阵列区的外围中的晶体管的金属触点。在所述集成工艺流程中,能通过转换形成在所述存储器阵列区及所述存储器阵列区的所述外围上的多晶硅来形成所述金属硅化物。</abstract><oa>free_for_read</oa></addata></record> |
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subjects | ELECTRICITY |
title | Integrated memory array and peripheral metal silicide |
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