Novel DEMOS device structure using high dielectric constant material

The invention discloses a novel DEMOS device structure using a high dielectric constant material. The device comprises a substrate region, a channel region, a drift region and a gate structure, the gate structure is composed of a gate oxide layer, a polycrystalline silicon gate and a gate side wall which are sequentially formed on the surface of the substrate region, and a dielectric layer with a high k value is added between the polycrystalline silicon gate and the gate oxide layer and used for compensating an electric field in the device and improving the voltage resistance of the device. The dielectric constant of the added high-k layer is higher, and the compensation of the high-k layer to the electric field is beneficial to enabling the electric field distribution in the device to be more uniform and optimized. This optimized distribution helps to reduce specific on-resistance by reducing electric field concentration in critical regions, thereby achieving better overall performance. The method is similar