Wafer and wafer manufacturing method

The invention relates to the technical field of semiconductors, and discloses a wafer, which comprises a wafer body, and the cutting groove is formed in the wafer body along the cutting channel of the wafer body. The cutting grooves are formed in the cutting channels of the wafer body. Due to the fa...

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Hauptverfasser: LI KAILIANG, ZHENG PUGUANG, ZHANG JUANRONG
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ZHENG PUGUANG
ZHANG JUANRONG
description The invention relates to the technical field of semiconductors, and discloses a wafer, which comprises a wafer body, and the cutting groove is formed in the wafer body along the cutting channel of the wafer body. The cutting grooves are formed in the cutting channels of the wafer body. Due to the fact that stress in the cutting process can be released through the cutting grooves, accumulation of the stress in the cutting process is reduced. Therefore, when the chip on the wafer provided by the invention is cut, the risk of generating cracks at the edge and corner positions of the chip is low, and the risk of chip damage is low. The invention further discloses a manufacturing method of the wafer. 本申请涉及半导体技术领域,公开一种晶圆,包括:晶圆本体;切割槽,沿晶圆本体的切割道开设于晶圆本体。本申请中在晶圆本体的切割道上开设了切割槽。由于切割槽可以使切割过程中的应力得到释放,减少切割过程中应力的累积。所以在对本申请提供的晶圆上的芯片进行切割时,芯片边缘及边角位置产生裂纹的风险较低,芯片损坏的风险较低。本申请还公开一种晶圆的制作方法。
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The cutting grooves are formed in the cutting channels of the wafer body. Due to the fact that stress in the cutting process can be released through the cutting grooves, accumulation of the stress in the cutting process is reduced. Therefore, when the chip on the wafer provided by the invention is cut, the risk of generating cracks at the edge and corner positions of the chip is low, and the risk of chip damage is low. The invention further discloses a manufacturing method of the wafer. 本申请涉及半导体技术领域,公开一种晶圆,包括:晶圆本体;切割槽,沿晶圆本体的切割道开设于晶圆本体。本申请中在晶圆本体的切割道上开设了切割槽。由于切割槽可以使切割过程中的应力得到释放,减少切割过程中应力的累积。所以在对本申请提供的晶圆上的芯片进行切割时,芯片边缘及边角位置产生裂纹的风险较低,芯片损坏的风险较低。本申请还公开一种晶圆的制作方法。</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240206&amp;DB=EPODOC&amp;CC=CN&amp;NR=117524983A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240206&amp;DB=EPODOC&amp;CC=CN&amp;NR=117524983A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LI KAILIANG</creatorcontrib><creatorcontrib>ZHENG PUGUANG</creatorcontrib><creatorcontrib>ZHANG JUANRONG</creatorcontrib><title>Wafer and wafer manufacturing method</title><description>The invention relates to the technical field of semiconductors, and discloses a wafer, which comprises a wafer body, and the cutting groove is formed in the wafer body along the cutting channel of the wafer body. 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ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Wafer and wafer manufacturing method
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