GaN HEMT cascade type device multi-layer stacked sealing structure and preparation method thereof
The invention relates to the technical field of semiconductors, and discloses a GaN HEMT cascade type device multi-layer stacked sealing structure and a preparation method thereof, and the GaN HEMT cascade type device multi-layer stacked sealing structure comprises a GaN chip, a substrate and an MOS...
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| creator | ZHANG QI LIANG HUINAN TIAN MAOKANG WANG RONGHUA REN YONGSHUO |
| description | The invention relates to the technical field of semiconductors, and discloses a GaN HEMT cascade type device multi-layer stacked sealing structure and a preparation method thereof, and the GaN HEMT cascade type device multi-layer stacked sealing structure comprises a GaN chip, a substrate and an MOS chip. The middle of the substrate is an insulating layer, and conducting layers are arranged on the front and back surfaces of the substrate; the GaN chip is provided with a source electrode window, and any point in the source electrode window is configured as a source electrode of the GaN chip; the substrate and the MOS chip are of a laminated structure, the laminated structure is arranged in the source window, and the size of the source window is larger than that of the laminated structure; the stacked structure is arranged on the source electrode window, and the substrate and the MOS chip are configured to be electrically connected with the GaN chip, so that the source electrode of the MOS chip is electrically |
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The middle of the substrate is an insulating layer, and conducting layers are arranged on the front and back surfaces of the substrate; the GaN chip is provided with a source electrode window, and any point in the source electrode window is configured as a source electrode of the GaN chip; the substrate and the MOS chip are of a laminated structure, the laminated structure is arranged in the source window, and the size of the source window is larger than that of the laminated structure; the stacked structure is arranged on the source electrode window, and the substrate and the MOS chip are configured to be electrically connected with the GaN chip, so that the source electrode of the MOS chip is electrically</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEOgjAURmEWB6O-w_UBGAgk6mgIyiITO7lpf6SxtE17MeHtdfABnE6-5GwzvnNHbfPoSXFSrEGyBpDG2yjQvFgxueUVkZKwekFTAlvjnl_HRckSQew0hYjAkcV4RzNk8ppkQoQf99lmZJtw-HWXHW9NX7c5gh-QAis4yFB3RXGqynN5qa7lP88HojY9YA</recordid><startdate>20240123</startdate><enddate>20240123</enddate><creator>ZHANG QI</creator><creator>LIANG HUINAN</creator><creator>TIAN MAOKANG</creator><creator>WANG RONGHUA</creator><creator>REN YONGSHUO</creator><scope>EVB</scope></search><sort><creationdate>20240123</creationdate><title>GaN HEMT cascade type device multi-layer stacked sealing structure and preparation method thereof</title><author>ZHANG QI ; LIANG HUINAN ; TIAN MAOKANG ; WANG RONGHUA ; REN YONGSHUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN117438394A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ZHANG QI</creatorcontrib><creatorcontrib>LIANG HUINAN</creatorcontrib><creatorcontrib>TIAN MAOKANG</creatorcontrib><creatorcontrib>WANG RONGHUA</creatorcontrib><creatorcontrib>REN YONGSHUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZHANG QI</au><au>LIANG HUINAN</au><au>TIAN MAOKANG</au><au>WANG RONGHUA</au><au>REN YONGSHUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>GaN HEMT cascade type device multi-layer stacked sealing structure and preparation method thereof</title><date>2024-01-23</date><risdate>2024</risdate><abstract>The invention relates to the technical field of semiconductors, and discloses a GaN HEMT cascade type device multi-layer stacked sealing structure and a preparation method thereof, and the GaN HEMT cascade type device multi-layer stacked sealing structure comprises a GaN chip, a substrate and an MOS chip. The middle of the substrate is an insulating layer, and conducting layers are arranged on the front and back surfaces of the substrate; the GaN chip is provided with a source electrode window, and any point in the source electrode window is configured as a source electrode of the GaN chip; the substrate and the MOS chip are of a laminated structure, the laminated structure is arranged in the source window, and the size of the source window is larger than that of the laminated structure; the stacked structure is arranged on the source electrode window, and the substrate and the MOS chip are configured to be electrically connected with the GaN chip, so that the source electrode of the MOS chip is electrically</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | GaN HEMT cascade type device multi-layer stacked sealing structure and preparation method thereof |
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