Semiconductor memory device

The semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gate circuit, and a control logic circuit. The memory cell array includes a plurality of sub-array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with the memory controller through the I/O pad. An I/O gate circuit is connected to a data I/O buffer through a data bus and to a memory cell array through a data I/O line, and a mapping relationship between sub-array blocks and I/O pads is programmed based on a mapping control signal, thereby reducing uncorrectable errors detected by an error correction code engine in the memory controller. The control logic circuit generates a mapping control signal based on identifier information indicating a type of a central processing unit of the storage controller. 半导体存储器件包括存储单元阵列、数据输入/输出(I/O)缓冲器、I/0选通电路和控制逻辑电路。存储单元阵列包括沿第一方向和第二方向布置的多个子阵列块。数据I/0缓冲器通过I/O焊盘与存储控制器交换用户数据。I/O选通电路通过数据总线连接到数据I/O缓冲器，并且通过数据I/O线连接到存储单元阵列，以及基于映射控制信号，