Wiring method and device for FPGA (Field Programmable Gate Array)
The invention discloses an FPGA wiring method and device, and the method comprises the steps: obtaining the connection rule information between each type of wiring node in a to-be-wired FPGA device and other types of wiring nodes, and enabling the connection rule information to serve as the wiring r...
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creator | MIN XIANGWEI SONG GUOMIN LI HAIBO WANG TONGTONG FAN ZHAO WANG XINGGANG WEI SHANJU |
description | The invention discloses an FPGA wiring method and device, and the method comprises the steps: obtaining the connection rule information between each type of wiring node in a to-be-wired FPGA device and other types of wiring nodes, and enabling the connection rule information to serve as the wiring rule information of the type of wiring node; and performing FPGA wiring on the logic resources with the connection relationship in the arranged netlist by using the wiring rule information of all types of wiring nodes and the position information of the logic resources in the arranged netlist. According to the embodiment of the invention, FPGA wiring can be carried out on the logic resources with the connection relationship in the arranged netlist through the connection rule information corresponding to each type of wiring nodes, so that establishment of a wiring resource directed graph is avoided, and memory overhead caused by establishment of the wiring resource directed graph is saved; and moreover, the iteration |
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According to the embodiment of the invention, FPGA wiring can be carried out on the logic resources with the connection relationship in the arranged netlist through the connection rule information corresponding to each type of wiring nodes, so that establishment of a wiring resource directed graph is avoided, and memory overhead caused by establishment of the wiring resource directed graph is saved; and moreover, the iteration</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231017&DB=EPODOC&CC=CN&NR=116894424A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231017&DB=EPODOC&CC=CN&NR=116894424A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MIN XIANGWEI</creatorcontrib><creatorcontrib>SONG GUOMIN</creatorcontrib><creatorcontrib>LI HAIBO</creatorcontrib><creatorcontrib>WANG TONGTONG</creatorcontrib><creatorcontrib>FAN ZHAO</creatorcontrib><creatorcontrib>WANG XINGGANG</creatorcontrib><creatorcontrib>WEI SHANJU</creatorcontrib><title>Wiring method and device for FPGA (Field Programmable Gate Array)</title><description>The invention discloses an FPGA wiring method and device, and the method comprises the steps: obtaining the connection rule information between each type of wiring node in a to-be-wired FPGA device and other types of wiring nodes, and enabling the connection rule information to serve as the wiring rule information of the type of wiring node; and performing FPGA wiring on the logic resources with the connection relationship in the arranged netlist by using the wiring rule information of all types of wiring nodes and the position information of the logic resources in the arranged netlist. According to the embodiment of the invention, FPGA wiring can be carried out on the logic resources with the connection relationship in the arranged netlist through the connection rule information corresponding to each type of wiring nodes, so that establishment of a wiring resource directed graph is avoided, and memory overhead caused by establishment of the wiring resource directed graph is saved; and moreover, the iteration</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAMzyzKzEtXyE0tychPUUjMS1FISS3LTE5VSMsvUnALcHdU0HDLTM1JUQgoyk8vSszNTUzKSVVwTyxJVXAsKkqs1ORhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfHOfoaGZhaWJiZGJo7GxKgBAC_XL90</recordid><startdate>20231017</startdate><enddate>20231017</enddate><creator>MIN XIANGWEI</creator><creator>SONG GUOMIN</creator><creator>LI HAIBO</creator><creator>WANG TONGTONG</creator><creator>FAN ZHAO</creator><creator>WANG XINGGANG</creator><creator>WEI SHANJU</creator><scope>EVB</scope></search><sort><creationdate>20231017</creationdate><title>Wiring method and device for FPGA (Field Programmable Gate Array)</title><author>MIN XIANGWEI ; SONG GUOMIN ; LI HAIBO ; WANG TONGTONG ; FAN ZHAO ; WANG XINGGANG ; WEI SHANJU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116894424A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MIN XIANGWEI</creatorcontrib><creatorcontrib>SONG GUOMIN</creatorcontrib><creatorcontrib>LI HAIBO</creatorcontrib><creatorcontrib>WANG TONGTONG</creatorcontrib><creatorcontrib>FAN ZHAO</creatorcontrib><creatorcontrib>WANG XINGGANG</creatorcontrib><creatorcontrib>WEI SHANJU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MIN XIANGWEI</au><au>SONG GUOMIN</au><au>LI HAIBO</au><au>WANG TONGTONG</au><au>FAN ZHAO</au><au>WANG XINGGANG</au><au>WEI SHANJU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Wiring method and device for FPGA (Field Programmable Gate Array)</title><date>2023-10-17</date><risdate>2023</risdate><abstract>The invention discloses an FPGA wiring method and device, and the method comprises the steps: obtaining the connection rule information between each type of wiring node in a to-be-wired FPGA device and other types of wiring nodes, and enabling the connection rule information to serve as the wiring rule information of the type of wiring node; and performing FPGA wiring on the logic resources with the connection relationship in the arranged netlist by using the wiring rule information of all types of wiring nodes and the position information of the logic resources in the arranged netlist. According to the embodiment of the invention, FPGA wiring can be carried out on the logic resources with the connection relationship in the arranged netlist through the connection rule information corresponding to each type of wiring nodes, so that establishment of a wiring resource directed graph is avoided, and memory overhead caused by establishment of the wiring resource directed graph is saved; and moreover, the iteration</abstract><oa>free_for_read</oa></addata></record> |
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language | chi ; eng |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Wiring method and device for FPGA (Field Programmable Gate Array) |
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