Cavity packaging structure and forming method thereof
The invention discloses a cavity packaging structure and a forming method thereof, the cavity packaging structure comprises a metal substrate, the metal substrate comprises a middle area and an edge area surrounding the middle area, the middle area comprises a mounting area, a causeway structure is...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | LIU TING YU KAIYUAN ZHANG YUESHENG PU HU |
| description | The invention discloses a cavity packaging structure and a forming method thereof, the cavity packaging structure comprises a metal substrate, the metal substrate comprises a middle area and an edge area surrounding the middle area, the middle area comprises a mounting area, a causeway structure is formed on the edge area of the upper surface of the metal substrate, the causeway structure surrounds the middle area, and the surface of the surface of the metal substrate is provided with a cavity; pins extending to two sides are arranged in the causeway structure; the annular groove is positioned in the metal substrate in the middle area and surrounds the mounting area; the first buffer layer is located in the annular groove, and the thermal expansion coefficient of the first buffer layer is smaller than that of the metal substrate; the semiconductor chip is mounted on the upper surface of the mounting area and is electrically connected with the pins through metal leads; the upper cover is attached to the causew |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116864453A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116864453A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116864453A3</originalsourceid><addsrcrecordid>eNrjZDB1TizLLKlUKEhMzk5Mz8xLVyguKSpNLiktSlVIzEtRSMsvygWJ5qaWZOSnKJRkpBal5qfxMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjUYqBhqXmpJfHOfoaGZhZmJiamxo7GxKgBAIqFLYE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Cavity packaging structure and forming method thereof</title><source>esp@cenet</source><creator>LIU TING ; YU KAIYUAN ; ZHANG YUESHENG ; PU HU</creator><creatorcontrib>LIU TING ; YU KAIYUAN ; ZHANG YUESHENG ; PU HU</creatorcontrib><description>The invention discloses a cavity packaging structure and a forming method thereof, the cavity packaging structure comprises a metal substrate, the metal substrate comprises a middle area and an edge area surrounding the middle area, the middle area comprises a mounting area, a causeway structure is formed on the edge area of the upper surface of the metal substrate, the causeway structure surrounds the middle area, and the surface of the surface of the metal substrate is provided with a cavity; pins extending to two sides are arranged in the causeway structure; the annular groove is positioned in the metal substrate in the middle area and surrounds the mounting area; the first buffer layer is located in the annular groove, and the thermal expansion coefficient of the first buffer layer is smaller than that of the metal substrate; the semiconductor chip is mounted on the upper surface of the mounting area and is electrically connected with the pins through metal leads; the upper cover is attached to the causew</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231010&DB=EPODOC&CC=CN&NR=116864453A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231010&DB=EPODOC&CC=CN&NR=116864453A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIU TING</creatorcontrib><creatorcontrib>YU KAIYUAN</creatorcontrib><creatorcontrib>ZHANG YUESHENG</creatorcontrib><creatorcontrib>PU HU</creatorcontrib><title>Cavity packaging structure and forming method thereof</title><description>The invention discloses a cavity packaging structure and a forming method thereof, the cavity packaging structure comprises a metal substrate, the metal substrate comprises a middle area and an edge area surrounding the middle area, the middle area comprises a mounting area, a causeway structure is formed on the edge area of the upper surface of the metal substrate, the causeway structure surrounds the middle area, and the surface of the surface of the metal substrate is provided with a cavity; pins extending to two sides are arranged in the causeway structure; the annular groove is positioned in the metal substrate in the middle area and surrounds the mounting area; the first buffer layer is located in the annular groove, and the thermal expansion coefficient of the first buffer layer is smaller than that of the metal substrate; the semiconductor chip is mounted on the upper surface of the mounting area and is electrically connected with the pins through metal leads; the upper cover is attached to the causew</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB1TizLLKlUKEhMzk5Mz8xLVyguKSpNLiktSlVIzEtRSMsvygWJ5qaWZOSnKJRkpBal5qfxMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjUYqBhqXmpJfHOfoaGZhZmJiamxo7GxKgBAIqFLYE</recordid><startdate>20231010</startdate><enddate>20231010</enddate><creator>LIU TING</creator><creator>YU KAIYUAN</creator><creator>ZHANG YUESHENG</creator><creator>PU HU</creator><scope>EVB</scope></search><sort><creationdate>20231010</creationdate><title>Cavity packaging structure and forming method thereof</title><author>LIU TING ; YU KAIYUAN ; ZHANG YUESHENG ; PU HU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116864453A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LIU TING</creatorcontrib><creatorcontrib>YU KAIYUAN</creatorcontrib><creatorcontrib>ZHANG YUESHENG</creatorcontrib><creatorcontrib>PU HU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIU TING</au><au>YU KAIYUAN</au><au>ZHANG YUESHENG</au><au>PU HU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Cavity packaging structure and forming method thereof</title><date>2023-10-10</date><risdate>2023</risdate><abstract>The invention discloses a cavity packaging structure and a forming method thereof, the cavity packaging structure comprises a metal substrate, the metal substrate comprises a middle area and an edge area surrounding the middle area, the middle area comprises a mounting area, a causeway structure is formed on the edge area of the upper surface of the metal substrate, the causeway structure surrounds the middle area, and the surface of the surface of the metal substrate is provided with a cavity; pins extending to two sides are arranged in the causeway structure; the annular groove is positioned in the metal substrate in the middle area and surrounds the mounting area; the first buffer layer is located in the annular groove, and the thermal expansion coefficient of the first buffer layer is smaller than that of the metal substrate; the semiconductor chip is mounted on the upper surface of the mounting area and is electrically connected with the pins through metal leads; the upper cover is attached to the causew</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN116864453A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Cavity packaging structure and forming method thereof |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-15T07%3A49%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LIU%20TING&rft.date=2023-10-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN116864453A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |