Packaging structure, manufacturing method thereof and electronic equipment

The invention relates to a packaging structure, a manufacturing method thereof and electronic equipment. The packaging structure comprises at least two bare chips; the first plastic package layer wraps each bare chip and exposes the plurality of first bumps of each bare chip; a first connecting laye...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: JIANG SHANGXUAN, ZHAO NAN, HU XIAO
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator JIANG SHANGXUAN
ZHAO NAN
HU XIAO
description The invention relates to a packaging structure, a manufacturing method thereof and electronic equipment. The packaging structure comprises at least two bare chips; the first plastic package layer wraps each bare chip and exposes the plurality of first bumps of each bare chip; a first connecting layer and a second connecting layer, each connecting layer comprises a substrate and a rewiring layer which covers the first surface of the substrate and is electrically connected with a plurality of via holes of the substrate, the substrate is a glass substrate, and the plurality of connecting layers comprise a plurality of connecting layers; the first connecting layer is arranged on the surface, where the plurality of first bumps of the bare chips are exposed, of the first plastic packaging layer, the plurality of first bumps of the bare chips are electrically connected to the rewiring layer in the first connecting layer, and the space between the first connecting layer and each bare chip is filled with the first fil
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116802794A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116802794A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116802794A3</originalsourceid><addsrcrecordid>eNrjZPAKSEzOTkzPzEtXKC4pKk0uKS1K1VHITcwrTUsEcUASuaklGfkpCiUZqUWp-WkKiXkpCqk5qcklRfl5mckKqYWlmQW5qXklPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7Uk3tnP0NDMwsDI3NLE0ZgYNQB48TXU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Packaging structure, manufacturing method thereof and electronic equipment</title><source>esp@cenet</source><creator>JIANG SHANGXUAN ; ZHAO NAN ; HU XIAO</creator><creatorcontrib>JIANG SHANGXUAN ; ZHAO NAN ; HU XIAO</creatorcontrib><description>The invention relates to a packaging structure, a manufacturing method thereof and electronic equipment. The packaging structure comprises at least two bare chips; the first plastic package layer wraps each bare chip and exposes the plurality of first bumps of each bare chip; a first connecting layer and a second connecting layer, each connecting layer comprises a substrate and a rewiring layer which covers the first surface of the substrate and is electrically connected with a plurality of via holes of the substrate, the substrate is a glass substrate, and the plurality of connecting layers comprise a plurality of connecting layers; the first connecting layer is arranged on the surface, where the plurality of first bumps of the bare chips are exposed, of the first plastic packaging layer, the plurality of first bumps of the bare chips are electrically connected to the rewiring layer in the first connecting layer, and the space between the first connecting layer and each bare chip is filled with the first fil</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230922&amp;DB=EPODOC&amp;CC=CN&amp;NR=116802794A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230922&amp;DB=EPODOC&amp;CC=CN&amp;NR=116802794A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JIANG SHANGXUAN</creatorcontrib><creatorcontrib>ZHAO NAN</creatorcontrib><creatorcontrib>HU XIAO</creatorcontrib><title>Packaging structure, manufacturing method thereof and electronic equipment</title><description>The invention relates to a packaging structure, a manufacturing method thereof and electronic equipment. The packaging structure comprises at least two bare chips; the first plastic package layer wraps each bare chip and exposes the plurality of first bumps of each bare chip; a first connecting layer and a second connecting layer, each connecting layer comprises a substrate and a rewiring layer which covers the first surface of the substrate and is electrically connected with a plurality of via holes of the substrate, the substrate is a glass substrate, and the plurality of connecting layers comprise a plurality of connecting layers; the first connecting layer is arranged on the surface, where the plurality of first bumps of the bare chips are exposed, of the first plastic packaging layer, the plurality of first bumps of the bare chips are electrically connected to the rewiring layer in the first connecting layer, and the space between the first connecting layer and each bare chip is filled with the first fil</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAKSEzOTkzPzEtXKC4pKk0uKS1K1VHITcwrTUsEcUASuaklGfkpCiUZqUWp-WkKiXkpCqk5qcklRfl5mckKqYWlmQW5qXklPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7Uk3tnP0NDMwsDI3NLE0ZgYNQB48TXU</recordid><startdate>20230922</startdate><enddate>20230922</enddate><creator>JIANG SHANGXUAN</creator><creator>ZHAO NAN</creator><creator>HU XIAO</creator><scope>EVB</scope></search><sort><creationdate>20230922</creationdate><title>Packaging structure, manufacturing method thereof and electronic equipment</title><author>JIANG SHANGXUAN ; ZHAO NAN ; HU XIAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116802794A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JIANG SHANGXUAN</creatorcontrib><creatorcontrib>ZHAO NAN</creatorcontrib><creatorcontrib>HU XIAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JIANG SHANGXUAN</au><au>ZHAO NAN</au><au>HU XIAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Packaging structure, manufacturing method thereof and electronic equipment</title><date>2023-09-22</date><risdate>2023</risdate><abstract>The invention relates to a packaging structure, a manufacturing method thereof and electronic equipment. The packaging structure comprises at least two bare chips; the first plastic package layer wraps each bare chip and exposes the plurality of first bumps of each bare chip; a first connecting layer and a second connecting layer, each connecting layer comprises a substrate and a rewiring layer which covers the first surface of the substrate and is electrically connected with a plurality of via holes of the substrate, the substrate is a glass substrate, and the plurality of connecting layers comprise a plurality of connecting layers; the first connecting layer is arranged on the surface, where the plurality of first bumps of the bare chips are exposed, of the first plastic packaging layer, the plurality of first bumps of the bare chips are electrically connected to the rewiring layer in the first connecting layer, and the space between the first connecting layer and each bare chip is filled with the first fil</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN116802794A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Packaging structure, manufacturing method thereof and electronic equipment
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T23%3A37%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JIANG%20SHANGXUAN&rft.date=2023-09-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN116802794A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true