Camera link video acquisition and conversion method and device based on FPGA (Field Programmable Gate Array)
The invention relates to the field of video acquisition and display, and discloses an FPGA (Field Programmable Gate Array)-based camera video acquisition and conversion method, which comprises the following steps of: transmitting four groups of serial lvds data transmitted by a camera to an FPGA dif...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | CHEN WEIDONG LIU ZHAOWEI GE CHENG DING JINQI ZHENG MINHONG LI HAO |
| description | The invention relates to the field of video acquisition and display, and discloses an FPGA (Field Programmable Gate Array)-based camera video acquisition and conversion method, which comprises the following steps of: transmitting four groups of serial lvds data transmitted by a camera to an FPGA differential pin; a decoder is designed in the FPGA to recover the four groups of serial lvds data into 28-bit parallel image data; combining the 28-bit parallel image data based on a camera link protocol to generate a video signal in a standard image format, including an image data signal and a line-field synchronous control signal; and caching the video signal, and respectively outputting the video signal to an HDMI (High Definition Multimedia Interface) display and a PAL (Programmable Logic Controller) display according to a preset format. According to the invention, the video image collected by the camera is decoded through the FPGA, and the decoded video data can be directly displayed on the PAL or HDMI display, |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116760995A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116760995A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116760995A3</originalsourceid><addsrcrecordid>eNqNirsKwkAUBdNYiPoP104LwSBGUoZgYiUp7MPN7lEX9xF314B_7wM_wOowM2ec6JINPJNW9kaDknDE4v5QQUXlLLGVJJwd4MMHDeLVya-VGJQAdRwg6Z2qpi5oUSloSY13F8_GcKdBNUdQ4T0_l9NkdGYdMPvtJJlX-1N5WKF3LULPAhaxLY9pmu2ydZ5vi80_nxdeN0An</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Camera link video acquisition and conversion method and device based on FPGA (Field Programmable Gate Array)</title><source>esp@cenet</source><creator>CHEN WEIDONG ; LIU ZHAOWEI ; GE CHENG ; DING JINQI ; ZHENG MINHONG ; LI HAO</creator><creatorcontrib>CHEN WEIDONG ; LIU ZHAOWEI ; GE CHENG ; DING JINQI ; ZHENG MINHONG ; LI HAO</creatorcontrib><description>The invention relates to the field of video acquisition and display, and discloses an FPGA (Field Programmable Gate Array)-based camera video acquisition and conversion method, which comprises the following steps of: transmitting four groups of serial lvds data transmitted by a camera to an FPGA differential pin; a decoder is designed in the FPGA to recover the four groups of serial lvds data into 28-bit parallel image data; combining the 28-bit parallel image data based on a camera link protocol to generate a video signal in a standard image format, including an image data signal and a line-field synchronous control signal; and caching the video signal, and respectively outputting the video signal to an HDMI (High Definition Multimedia Interface) display and a PAL (Programmable Logic Controller) display according to a preset format. According to the invention, the video image collected by the camera is decoded through the FPGA, and the decoded video data can be directly displayed on the PAL or HDMI display,</description><language>chi ; eng</language><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL ; CONTROLLING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS ; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ; PHYSICS ; PICTORIAL COMMUNICATION, e.g. TELEVISION ; REGULATING</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230915&DB=EPODOC&CC=CN&NR=116760995A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230915&DB=EPODOC&CC=CN&NR=116760995A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHEN WEIDONG</creatorcontrib><creatorcontrib>LIU ZHAOWEI</creatorcontrib><creatorcontrib>GE CHENG</creatorcontrib><creatorcontrib>DING JINQI</creatorcontrib><creatorcontrib>ZHENG MINHONG</creatorcontrib><creatorcontrib>LI HAO</creatorcontrib><title>Camera link video acquisition and conversion method and device based on FPGA (Field Programmable Gate Array)</title><description>The invention relates to the field of video acquisition and display, and discloses an FPGA (Field Programmable Gate Array)-based camera video acquisition and conversion method, which comprises the following steps of: transmitting four groups of serial lvds data transmitted by a camera to an FPGA differential pin; a decoder is designed in the FPGA to recover the four groups of serial lvds data into 28-bit parallel image data; combining the 28-bit parallel image data based on a camera link protocol to generate a video signal in a standard image format, including an image data signal and a line-field synchronous control signal; and caching the video signal, and respectively outputting the video signal to an HDMI (High Definition Multimedia Interface) display and a PAL (Programmable Logic Controller) display according to a preset format. According to the invention, the video image collected by the camera is decoded through the FPGA, and the decoded video data can be directly displayed on the PAL or HDMI display,</description><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL</subject><subject>CONTROLLING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</subject><subject>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</subject><subject>PHYSICS</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><subject>REGULATING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNirsKwkAUBdNYiPoP104LwSBGUoZgYiUp7MPN7lEX9xF314B_7wM_wOowM2ec6JINPJNW9kaDknDE4v5QQUXlLLGVJJwd4MMHDeLVya-VGJQAdRwg6Z2qpi5oUSloSY13F8_GcKdBNUdQ4T0_l9NkdGYdMPvtJJlX-1N5WKF3LULPAhaxLY9pmu2ydZ5vi80_nxdeN0An</recordid><startdate>20230915</startdate><enddate>20230915</enddate><creator>CHEN WEIDONG</creator><creator>LIU ZHAOWEI</creator><creator>GE CHENG</creator><creator>DING JINQI</creator><creator>ZHENG MINHONG</creator><creator>LI HAO</creator><scope>EVB</scope></search><sort><creationdate>20230915</creationdate><title>Camera link video acquisition and conversion method and device based on FPGA (Field Programmable Gate Array)</title><author>CHEN WEIDONG ; LIU ZHAOWEI ; GE CHENG ; DING JINQI ; ZHENG MINHONG ; LI HAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116760995A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>CONTROL OR REGULATING SYSTEMS IN GENERAL</topic><topic>CONTROLLING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</topic><topic>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</topic><topic>PHYSICS</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><topic>REGULATING</topic><toplevel>online_resources</toplevel><creatorcontrib>CHEN WEIDONG</creatorcontrib><creatorcontrib>LIU ZHAOWEI</creatorcontrib><creatorcontrib>GE CHENG</creatorcontrib><creatorcontrib>DING JINQI</creatorcontrib><creatorcontrib>ZHENG MINHONG</creatorcontrib><creatorcontrib>LI HAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN WEIDONG</au><au>LIU ZHAOWEI</au><au>GE CHENG</au><au>DING JINQI</au><au>ZHENG MINHONG</au><au>LI HAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Camera link video acquisition and conversion method and device based on FPGA (Field Programmable Gate Array)</title><date>2023-09-15</date><risdate>2023</risdate><abstract>The invention relates to the field of video acquisition and display, and discloses an FPGA (Field Programmable Gate Array)-based camera video acquisition and conversion method, which comprises the following steps of: transmitting four groups of serial lvds data transmitted by a camera to an FPGA differential pin; a decoder is designed in the FPGA to recover the four groups of serial lvds data into 28-bit parallel image data; combining the 28-bit parallel image data based on a camera link protocol to generate a video signal in a standard image format, including an image data signal and a line-field synchronous control signal; and caching the video signal, and respectively outputting the video signal to an HDMI (High Definition Multimedia Interface) display and a PAL (Programmable Logic Controller) display according to a preset format. According to the invention, the video image collected by the camera is decoded through the FPGA, and the decoded video data can be directly displayed on the PAL or HDMI display,</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN116760995A |
| source | esp@cenet |
| subjects | CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS PICTORIAL COMMUNICATION, e.g. TELEVISION REGULATING |
| title | Camera link video acquisition and conversion method and device based on FPGA (Field Programmable Gate Array) |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T11%3A31%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHEN%20WEIDONG&rft.date=2023-09-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN116760995A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |