Timing sequence generation circuit

The invention relates to a timing sequence generation circuit. According to one embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time relative to each other; a first shift register including a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select one of the clock signals; and transmitting the selected clock signal to a clock signal input of the first shift register. 本公开涉及定时序列生成电路。根据一个实施例，一种定时序列生成电路包括：环形振荡器，其具有多个时钟信号输出，所述多个时钟信号输出被配置为提供在时间上相对于彼此延迟的时钟信号；第一移位寄存器，包括触发器，所述触发器具有耦合到所述第一移位寄存器的时钟信号输入的时钟输入和耦合到所述第一移位寄存器的输出的输出；以及第一电路，其被配置为：从所述时钟信号中选择一个时钟信号；以及将所选择的时钟信号传送到第一移位寄存器的时钟信号输入。