Programmable logic circuit and method and device for dynamically rewriting programmable logic circuit

The invention discloses a programmable logic circuit and a method and device for dynamically rewriting the programmable logic circuit, and belongs to the field of digital logic circuits. The gate circuit is replaced by the dual-port SRAM, and after replacement, during time sequence verification, as...

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Hauptverfasser: FUKUSHIMA KEITA, SUN JINGHANG, KATSU MITSUNORI
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creator FUKUSHIMA KEITA
SUN JINGHANG
KATSU MITSUNORI
description The invention discloses a programmable logic circuit and a method and device for dynamically rewriting the programmable logic circuit, and belongs to the field of digital logic circuits. The gate circuit is replaced by the dual-port SRAM, and after replacement, during time sequence verification, as the calculation process does not exist in the dual-port SRAM, the input can be output as long as the input is received, so that the time sequence verification time is greatly shortened. In addition, no semiconductor or metal wiring exists in the dual-port SRAM, so that no extra current is consumed, and the current cost is reduced. Meanwhile, the first port of the dual-port SRAM can read the truth table to ensure the normal execution of the functions of the programmable logic circuit, and the second port of the dual-port SRAM can write in a new truth table, so that the internal logic of the programmable logic circuit is changed while the functions are executed, and the functions of the programmable logic circuit are
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116741230A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116741230A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116741230A3</originalsourceid><addsrcrecordid>eNqNjLsKwkAQAK-xEPUf1g8QPCNaS1CsxMI-rHubZOFebE4lfy-IrWA1UwwzNXzV1CmGgHfP4FMnBCRKDymA0UHg0if3UcdPIYY2KbgxYhBC70dQfqkUiR3kn6u5mbToB158OTPL0_FWn1ecU8NDRuLIpakv1u72W7up1ofqn-YNXoI_og</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Programmable logic circuit and method and device for dynamically rewriting programmable logic circuit</title><source>esp@cenet</source><creator>FUKUSHIMA KEITA ; SUN JINGHANG ; KATSU MITSUNORI</creator><creatorcontrib>FUKUSHIMA KEITA ; SUN JINGHANG ; KATSU MITSUNORI</creatorcontrib><description>The invention discloses a programmable logic circuit and a method and device for dynamically rewriting the programmable logic circuit, and belongs to the field of digital logic circuits. The gate circuit is replaced by the dual-port SRAM, and after replacement, during time sequence verification, as the calculation process does not exist in the dual-port SRAM, the input can be output as long as the input is received, so that the time sequence verification time is greatly shortened. In addition, no semiconductor or metal wiring exists in the dual-port SRAM, so that no extra current is consumed, and the current cost is reduced. Meanwhile, the first port of the dual-port SRAM can read the truth table to ensure the normal execution of the functions of the programmable logic circuit, and the second port of the dual-port SRAM can write in a new truth table, so that the internal logic of the programmable logic circuit is changed while the functions are executed, and the functions of the programmable logic circuit are</description><language>chi ; eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230912&amp;DB=EPODOC&amp;CC=CN&amp;NR=116741230A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230912&amp;DB=EPODOC&amp;CC=CN&amp;NR=116741230A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FUKUSHIMA KEITA</creatorcontrib><creatorcontrib>SUN JINGHANG</creatorcontrib><creatorcontrib>KATSU MITSUNORI</creatorcontrib><title>Programmable logic circuit and method and device for dynamically rewriting programmable logic circuit</title><description>The invention discloses a programmable logic circuit and a method and device for dynamically rewriting the programmable logic circuit, and belongs to the field of digital logic circuits. The gate circuit is replaced by the dual-port SRAM, and after replacement, during time sequence verification, as the calculation process does not exist in the dual-port SRAM, the input can be output as long as the input is received, so that the time sequence verification time is greatly shortened. In addition, no semiconductor or metal wiring exists in the dual-port SRAM, so that no extra current is consumed, and the current cost is reduced. Meanwhile, the first port of the dual-port SRAM can read the truth table to ensure the normal execution of the functions of the programmable logic circuit, and the second port of the dual-port SRAM can write in a new truth table, so that the internal logic of the programmable logic circuit is changed while the functions are executed, and the functions of the programmable logic circuit are</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLsKwkAQAK-xEPUf1g8QPCNaS1CsxMI-rHubZOFebE4lfy-IrWA1UwwzNXzV1CmGgHfP4FMnBCRKDymA0UHg0if3UcdPIYY2KbgxYhBC70dQfqkUiR3kn6u5mbToB158OTPL0_FWn1ecU8NDRuLIpakv1u72W7up1ofqn-YNXoI_og</recordid><startdate>20230912</startdate><enddate>20230912</enddate><creator>FUKUSHIMA KEITA</creator><creator>SUN JINGHANG</creator><creator>KATSU MITSUNORI</creator><scope>EVB</scope></search><sort><creationdate>20230912</creationdate><title>Programmable logic circuit and method and device for dynamically rewriting programmable logic circuit</title><author>FUKUSHIMA KEITA ; SUN JINGHANG ; KATSU MITSUNORI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116741230A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>FUKUSHIMA KEITA</creatorcontrib><creatorcontrib>SUN JINGHANG</creatorcontrib><creatorcontrib>KATSU MITSUNORI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FUKUSHIMA KEITA</au><au>SUN JINGHANG</au><au>KATSU MITSUNORI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Programmable logic circuit and method and device for dynamically rewriting programmable logic circuit</title><date>2023-09-12</date><risdate>2023</risdate><abstract>The invention discloses a programmable logic circuit and a method and device for dynamically rewriting the programmable logic circuit, and belongs to the field of digital logic circuits. The gate circuit is replaced by the dual-port SRAM, and after replacement, during time sequence verification, as the calculation process does not exist in the dual-port SRAM, the input can be output as long as the input is received, so that the time sequence verification time is greatly shortened. In addition, no semiconductor or metal wiring exists in the dual-port SRAM, so that no extra current is consumed, and the current cost is reduced. Meanwhile, the first port of the dual-port SRAM can read the truth table to ensure the normal execution of the functions of the programmable logic circuit, and the second port of the dual-port SRAM can write in a new truth table, so that the internal logic of the programmable logic circuit is changed while the functions are executed, and the functions of the programmable logic circuit are</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
title Programmable logic circuit and method and device for dynamically rewriting programmable logic circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T23%3A16%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=FUKUSHIMA%20KEITA&rft.date=2023-09-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN116741230A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true