Chip substrate netlist proofreading method, device, equipment and medium
The embodiment of the invention provides a chip substrate netlist proofreading method and device, equipment and a medium, and the method comprises the steps: converting an original chip substrate netlist into a pin layout diagram, enabling grids of the original chip substrate netlist to correspond t...
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| creator | LAI NAI GONG HUI HU QIUYONG WENG WEIMING |
| description | The embodiment of the invention provides a chip substrate netlist proofreading method and device, equipment and a medium, and the method comprises the steps: converting an original chip substrate netlist into a pin layout diagram, enabling grids of the original chip substrate netlist to correspond to pin points of the pin layout diagram, enabling the grids of the original chip substrate netlist to be provided with coordinates and grid names, and enabling the coordinates of the grids of the original chip substrate netlist to correspond to the pin points of the pin layout diagram; pin points of the pin layout diagram are provided with coordinates and grid names; adjusting pin points of the pin layout diagram to obtain an adjusted pin layout diagram; according to the adjusted coordinates and grid names of the pin points of the pin layout diagram, checking an original chip substrate netlist to obtain a checked chip substrate netlist; and by introducing grid names and coordinates for labeling, comparison and proof |
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pin points of the pin layout diagram are provided with coordinates and grid names; adjusting pin points of the pin layout diagram to obtain an adjusted pin layout diagram; according to the adjusted coordinates and grid names of the pin points of the pin layout diagram, checking an original chip substrate netlist to obtain a checked chip substrate netlist; and by introducing grid names and coordinates for labeling, comparison and proof</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230901&DB=EPODOC&CC=CN&NR=116681010A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230901&DB=EPODOC&CC=CN&NR=116681010A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LAI NAI</creatorcontrib><creatorcontrib>GONG HUI</creatorcontrib><creatorcontrib>HU QIUYONG</creatorcontrib><creatorcontrib>WENG WEIMING</creatorcontrib><title>Chip substrate netlist proofreading method, device, equipment and medium</title><description>The embodiment of the invention provides a chip substrate netlist proofreading method and device, equipment and a medium, and the method comprises the steps: converting an original chip substrate netlist into a pin layout diagram, enabling grids of the original chip substrate netlist to correspond to pin points of the pin layout diagram, enabling the grids of the original chip substrate netlist to be provided with coordinates and grid names, and enabling the coordinates of the grids of the original chip substrate netlist to correspond to the pin points of the pin layout diagram; pin points of the pin layout diagram are provided with coordinates and grid names; adjusting pin points of the pin layout diagram to obtain an adjusted pin layout diagram; according to the adjusted coordinates and grid names of the pin points of the pin layout diagram, checking an original chip substrate netlist to obtain a checked chip substrate netlist; and by introducing grid names and coordinates for labeling, comparison and proof</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjL0KwjAURrs4iPoO171Cg1BcS1A6ObmX2Hy1F5ofkxuf3w4-gNMZzuFsq17PHCmXZ5ZkBOQhC2ehmEKYEoxl_yIHmYOtyeLDI2rCu3B08ELG29VaLm5fbSazZBx-3FXH2_Wh-xNiGJCjGbG-B31Xqm0vqlFNd_6n-QK7jTRY</recordid><startdate>20230901</startdate><enddate>20230901</enddate><creator>LAI NAI</creator><creator>GONG HUI</creator><creator>HU QIUYONG</creator><creator>WENG WEIMING</creator><scope>EVB</scope></search><sort><creationdate>20230901</creationdate><title>Chip substrate netlist proofreading method, device, equipment and medium</title><author>LAI NAI ; GONG HUI ; HU QIUYONG ; WENG WEIMING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116681010A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>LAI NAI</creatorcontrib><creatorcontrib>GONG HUI</creatorcontrib><creatorcontrib>HU QIUYONG</creatorcontrib><creatorcontrib>WENG WEIMING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LAI NAI</au><au>GONG HUI</au><au>HU QIUYONG</au><au>WENG WEIMING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Chip substrate netlist proofreading method, device, equipment and medium</title><date>2023-09-01</date><risdate>2023</risdate><abstract>The embodiment of the invention provides a chip substrate netlist proofreading method and device, equipment and a medium, and the method comprises the steps: converting an original chip substrate netlist into a pin layout diagram, enabling grids of the original chip substrate netlist to correspond to pin points of the pin layout diagram, enabling the grids of the original chip substrate netlist to be provided with coordinates and grid names, and enabling the coordinates of the grids of the original chip substrate netlist to correspond to the pin points of the pin layout diagram; pin points of the pin layout diagram are provided with coordinates and grid names; adjusting pin points of the pin layout diagram to obtain an adjusted pin layout diagram; according to the adjusted coordinates and grid names of the pin points of the pin layout diagram, checking an original chip substrate netlist to obtain a checked chip substrate netlist; and by introducing grid names and coordinates for labeling, comparison and proof</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Chip substrate netlist proofreading method, device, equipment and medium |
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