Method for manufacturing double-step connecting hole by plasma and reactive ion etching
The invention discloses a method for manufacturing a double-step connecting hole by plasma and reactive ion etching. The method comprises the following steps of: 1) depositing a first dielectric layer (2) on a substrate (1); 2) depositing a second dielectric layer (3) on the first dielectric layer (...
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creator | GUO YIWEN XIAO TIAN RAN MING LIANG TAO LIANG KANGDI |
description | The invention discloses a method for manufacturing a double-step connecting hole by plasma and reactive ion etching. The method comprises the following steps of: 1) depositing a first dielectric layer (2) on a substrate (1); 2) depositing a second dielectric layer (3) on the first dielectric layer (2); 3) forming a connecting hole pattern on the second dielectric layer (3); 4) etching the connecting hole pattern of the second dielectric layer (3) to form a first step; 5) etching the first dielectric layer (2) to form a second step; 6) removing the photoetching pattern by using an etching process; and 7) depositing a metal layer (4), filling the connecting hole, and leading out the resistor. According to the method, the etching process is controlled, and the double-step connecting hole morphology is formed on the premise of single photoetching by utilizing the etching rate difference of two different media.
本发明公开一种用等离子体和反应离子刻蚀制造双台阶型连接孔的方法,步骤包括:1)在衬底(1)上淀积第一介质层(2);2)在第一介质层(2)上淀积第二介质层(3);3)在第二介质层(3)上形成连接孔图形;4)刻蚀 |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116646303A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116646303A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116646303A3</originalsourceid><addsrcrecordid>eNqNi7EKwkAQBdNYiPoP6wcEDJH0EiI2WgmWYXN58QKX3SN3J_j3RvADrAaGmXX2uCJa7WnQmSaWNLCJaR7lSb2mziEPEZ6MisDEr7bqQN2bvOMwMbH0NGOZxhdoVCFEY5dum60GdgG7HzfZ_tzc60sOry2CZwNBbOtbUVTVsSoP5an8p_kAbB058Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for manufacturing double-step connecting hole by plasma and reactive ion etching</title><source>esp@cenet</source><creator>GUO YIWEN ; XIAO TIAN ; RAN MING ; LIANG TAO ; LIANG KANGDI</creator><creatorcontrib>GUO YIWEN ; XIAO TIAN ; RAN MING ; LIANG TAO ; LIANG KANGDI</creatorcontrib><description>The invention discloses a method for manufacturing a double-step connecting hole by plasma and reactive ion etching. The method comprises the following steps of: 1) depositing a first dielectric layer (2) on a substrate (1); 2) depositing a second dielectric layer (3) on the first dielectric layer (2); 3) forming a connecting hole pattern on the second dielectric layer (3); 4) etching the connecting hole pattern of the second dielectric layer (3) to form a first step; 5) etching the first dielectric layer (2) to form a second step; 6) removing the photoetching pattern by using an etching process; and 7) depositing a metal layer (4), filling the connecting hole, and leading out the resistor. According to the method, the etching process is controlled, and the double-step connecting hole morphology is formed on the premise of single photoetching by utilizing the etching rate difference of two different media.
本发明公开一种用等离子体和反应离子刻蚀制造双台阶型连接孔的方法,步骤包括:1)在衬底(1)上淀积第一介质层(2);2)在第一介质层(2)上淀积第二介质层(3);3)在第二介质层(3)上形成连接孔图形;4)刻蚀</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230825&DB=EPODOC&CC=CN&NR=116646303A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230825&DB=EPODOC&CC=CN&NR=116646303A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GUO YIWEN</creatorcontrib><creatorcontrib>XIAO TIAN</creatorcontrib><creatorcontrib>RAN MING</creatorcontrib><creatorcontrib>LIANG TAO</creatorcontrib><creatorcontrib>LIANG KANGDI</creatorcontrib><title>Method for manufacturing double-step connecting hole by plasma and reactive ion etching</title><description>The invention discloses a method for manufacturing a double-step connecting hole by plasma and reactive ion etching. The method comprises the following steps of: 1) depositing a first dielectric layer (2) on a substrate (1); 2) depositing a second dielectric layer (3) on the first dielectric layer (2); 3) forming a connecting hole pattern on the second dielectric layer (3); 4) etching the connecting hole pattern of the second dielectric layer (3) to form a first step; 5) etching the first dielectric layer (2) to form a second step; 6) removing the photoetching pattern by using an etching process; and 7) depositing a metal layer (4), filling the connecting hole, and leading out the resistor. According to the method, the etching process is controlled, and the double-step connecting hole morphology is formed on the premise of single photoetching by utilizing the etching rate difference of two different media.
本发明公开一种用等离子体和反应离子刻蚀制造双台阶型连接孔的方法,步骤包括:1)在衬底(1)上淀积第一介质层(2);2)在第一介质层(2)上淀积第二介质层(3);3)在第二介质层(3)上形成连接孔图形;4)刻蚀</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7EKwkAQBdNYiPoP6wcEDJH0EiI2WgmWYXN58QKX3SN3J_j3RvADrAaGmXX2uCJa7WnQmSaWNLCJaR7lSb2mziEPEZ6MisDEr7bqQN2bvOMwMbH0NGOZxhdoVCFEY5dum60GdgG7HzfZ_tzc60sOry2CZwNBbOtbUVTVsSoP5an8p_kAbB058Q</recordid><startdate>20230825</startdate><enddate>20230825</enddate><creator>GUO YIWEN</creator><creator>XIAO TIAN</creator><creator>RAN MING</creator><creator>LIANG TAO</creator><creator>LIANG KANGDI</creator><scope>EVB</scope></search><sort><creationdate>20230825</creationdate><title>Method for manufacturing double-step connecting hole by plasma and reactive ion etching</title><author>GUO YIWEN ; XIAO TIAN ; RAN MING ; LIANG TAO ; LIANG KANGDI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116646303A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GUO YIWEN</creatorcontrib><creatorcontrib>XIAO TIAN</creatorcontrib><creatorcontrib>RAN MING</creatorcontrib><creatorcontrib>LIANG TAO</creatorcontrib><creatorcontrib>LIANG KANGDI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GUO YIWEN</au><au>XIAO TIAN</au><au>RAN MING</au><au>LIANG TAO</au><au>LIANG KANGDI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for manufacturing double-step connecting hole by plasma and reactive ion etching</title><date>2023-08-25</date><risdate>2023</risdate><abstract>The invention discloses a method for manufacturing a double-step connecting hole by plasma and reactive ion etching. The method comprises the following steps of: 1) depositing a first dielectric layer (2) on a substrate (1); 2) depositing a second dielectric layer (3) on the first dielectric layer (2); 3) forming a connecting hole pattern on the second dielectric layer (3); 4) etching the connecting hole pattern of the second dielectric layer (3) to form a first step; 5) etching the first dielectric layer (2) to form a second step; 6) removing the photoetching pattern by using an etching process; and 7) depositing a metal layer (4), filling the connecting hole, and leading out the resistor. According to the method, the etching process is controlled, and the double-step connecting hole morphology is formed on the premise of single photoetching by utilizing the etching rate difference of two different media.
本发明公开一种用等离子体和反应离子刻蚀制造双台阶型连接孔的方法,步骤包括:1)在衬底(1)上淀积第一介质层(2);2)在第一介质层(2)上淀积第二介质层(3);3)在第二介质层(3)上形成连接孔图形;4)刻蚀</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Method for manufacturing double-step connecting hole by plasma and reactive ion etching |
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