Semiconductor package with improved heat dissipation characteristics
A semiconductor package includes: a first interconnect structure; a first semiconductor chip disposed on the first interconnect structure and including a plurality of through vias and a first pad connected to the plurality of through vias; a second semiconductor chip disposed on the first interconne...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | LEE HEESEOK CHO YOUNG-SANG IM YUN-HYEOK |
description | A semiconductor package includes: a first interconnect structure; a first semiconductor chip disposed on the first interconnect structure and including a plurality of through vias and a first pad connected to the plurality of through vias; a second semiconductor chip disposed on the first interconnect structure, including a second pad electrically connected to the first pad, and having a size different from a size of the first semiconductor chip; a heat dissipation structure contacting and surrounding a side surface of at least one of the first semiconductor chip and the second semiconductor chip, and including a material having a thermal conductivity higher than a thermal conductivity of silicon; and a sealant surrounding a side surface of the heat dissipation structure.
一种半导体封装包括:第一互连结构;第一半导体芯片,设置在第一互连结构上并且包括多个贯通通路和连接到多个贯通通路的第一焊盘;第二半导体芯片,设置在第一互连结构上,包括电连接到第一焊盘的第二焊盘,并且具有与第一半导体芯片的尺寸不同的尺寸;散热结构,接触并围绕第一半导体芯片和第二半导体芯片中的至少一个的侧表面,并且包括具有比硅的热导率高的热导率的材料;以及围绕散热结构的侧表面的密封剂。 |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116364665A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116364665A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116364665A3</originalsourceid><addsrcrecordid>eNqNzDEOwjAMQNEsDAi4g3sAhqqQHbUgJhbYK8sxxIImUWzg-jBwAKa_PP25G848CeUUnmS5QkG6443hLRZBplLziwNERoMgqlLQJCegiBXJuIqakC7d7IoP5dWvC9cc9pf-uOaSR9bvlBPb2J_a1nd-4_121_1jPiMmM8k</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor package with improved heat dissipation characteristics</title><source>esp@cenet</source><creator>LEE HEESEOK ; CHO YOUNG-SANG ; IM YUN-HYEOK</creator><creatorcontrib>LEE HEESEOK ; CHO YOUNG-SANG ; IM YUN-HYEOK</creatorcontrib><description>A semiconductor package includes: a first interconnect structure; a first semiconductor chip disposed on the first interconnect structure and including a plurality of through vias and a first pad connected to the plurality of through vias; a second semiconductor chip disposed on the first interconnect structure, including a second pad electrically connected to the first pad, and having a size different from a size of the first semiconductor chip; a heat dissipation structure contacting and surrounding a side surface of at least one of the first semiconductor chip and the second semiconductor chip, and including a material having a thermal conductivity higher than a thermal conductivity of silicon; and a sealant surrounding a side surface of the heat dissipation structure.
一种半导体封装包括:第一互连结构;第一半导体芯片,设置在第一互连结构上并且包括多个贯通通路和连接到多个贯通通路的第一焊盘;第二半导体芯片,设置在第一互连结构上,包括电连接到第一焊盘的第二焊盘,并且具有与第一半导体芯片的尺寸不同的尺寸;散热结构,接触并围绕第一半导体芯片和第二半导体芯片中的至少一个的侧表面,并且包括具有比硅的热导率高的热导率的材料;以及围绕散热结构的侧表面的密封剂。</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230630&DB=EPODOC&CC=CN&NR=116364665A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230630&DB=EPODOC&CC=CN&NR=116364665A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE HEESEOK</creatorcontrib><creatorcontrib>CHO YOUNG-SANG</creatorcontrib><creatorcontrib>IM YUN-HYEOK</creatorcontrib><title>Semiconductor package with improved heat dissipation characteristics</title><description>A semiconductor package includes: a first interconnect structure; a first semiconductor chip disposed on the first interconnect structure and including a plurality of through vias and a first pad connected to the plurality of through vias; a second semiconductor chip disposed on the first interconnect structure, including a second pad electrically connected to the first pad, and having a size different from a size of the first semiconductor chip; a heat dissipation structure contacting and surrounding a side surface of at least one of the first semiconductor chip and the second semiconductor chip, and including a material having a thermal conductivity higher than a thermal conductivity of silicon; and a sealant surrounding a side surface of the heat dissipation structure.
一种半导体封装包括:第一互连结构;第一半导体芯片,设置在第一互连结构上并且包括多个贯通通路和连接到多个贯通通路的第一焊盘;第二半导体芯片,设置在第一互连结构上,包括电连接到第一焊盘的第二焊盘,并且具有与第一半导体芯片的尺寸不同的尺寸;散热结构,接触并围绕第一半导体芯片和第二半导体芯片中的至少一个的侧表面,并且包括具有比硅的热导率高的热导率的材料;以及围绕散热结构的侧表面的密封剂。</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzDEOwjAMQNEsDAi4g3sAhqqQHbUgJhbYK8sxxIImUWzg-jBwAKa_PP25G848CeUUnmS5QkG6443hLRZBplLziwNERoMgqlLQJCegiBXJuIqakC7d7IoP5dWvC9cc9pf-uOaSR9bvlBPb2J_a1nd-4_121_1jPiMmM8k</recordid><startdate>20230630</startdate><enddate>20230630</enddate><creator>LEE HEESEOK</creator><creator>CHO YOUNG-SANG</creator><creator>IM YUN-HYEOK</creator><scope>EVB</scope></search><sort><creationdate>20230630</creationdate><title>Semiconductor package with improved heat dissipation characteristics</title><author>LEE HEESEOK ; CHO YOUNG-SANG ; IM YUN-HYEOK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116364665A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LEE HEESEOK</creatorcontrib><creatorcontrib>CHO YOUNG-SANG</creatorcontrib><creatorcontrib>IM YUN-HYEOK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEE HEESEOK</au><au>CHO YOUNG-SANG</au><au>IM YUN-HYEOK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor package with improved heat dissipation characteristics</title><date>2023-06-30</date><risdate>2023</risdate><abstract>A semiconductor package includes: a first interconnect structure; a first semiconductor chip disposed on the first interconnect structure and including a plurality of through vias and a first pad connected to the plurality of through vias; a second semiconductor chip disposed on the first interconnect structure, including a second pad electrically connected to the first pad, and having a size different from a size of the first semiconductor chip; a heat dissipation structure contacting and surrounding a side surface of at least one of the first semiconductor chip and the second semiconductor chip, and including a material having a thermal conductivity higher than a thermal conductivity of silicon; and a sealant surrounding a side surface of the heat dissipation structure.
一种半导体封装包括:第一互连结构;第一半导体芯片,设置在第一互连结构上并且包括多个贯通通路和连接到多个贯通通路的第一焊盘;第二半导体芯片,设置在第一互连结构上,包括电连接到第一焊盘的第二焊盘,并且具有与第一半导体芯片的尺寸不同的尺寸;散热结构,接触并围绕第一半导体芯片和第二半导体芯片中的至少一个的侧表面,并且包括具有比硅的热导率高的热导率的材料;以及围绕散热结构的侧表面的密封剂。</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN116364665A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor package with improved heat dissipation characteristics |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T23%3A50%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LEE%20HEESEOK&rft.date=2023-06-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN116364665A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |