AXI4-Lite bus remote expansion method

AXI4-Lite bus remote expansion method

The invention relates to a remote extension method for an AXI4-Lite bus. In the read operation, the master-end FPGA gives an address on an AR channel of a master device interface, generates an RAP packet and sends the RAP packet to the slave-end FPGA, the slave-end FPGA extracts the address and send...

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Hauptverfasser: XU JIALIN, MA XIAODONG, WU QIONGZHI, XING TONGHE, ZHANG LIANJUAN
Format: Patent
Sprache:chi ; eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator XU JIALIN
MA XIAODONG
WU QIONGZHI
XING TONGHE
ZHANG LIANJUAN
description The invention relates to a remote extension method for an AXI4-Lite bus. In the read operation, the master-end FPGA gives an address on an AR channel of a master device interface, generates an RAP packet and sends the RAP packet to the slave-end FPGA, the slave-end FPGA extracts the address and sends the address to an AR channel of a slave device interface, the slave-end FPGA sends read data to an R channel of the interface, the slave-end FPGA generates an RP packet and sends the RP packet to the master-end FPGA, the master-end FPGA extracts the data and sends the data to an R channel of a master device, and the master device obtains the data from the R channel; in the write operation, the master end FPGA gives an address on a WR channel of the master device interface, gives data on a W channel, generates a WP packet and sends the WP packet to the slave end FPGA, the slave end FPGA extracts the address and the data and sends the address and the data to an AW channel and a W channel of the slave device interfa
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language chi ; eng
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title AXI4-Lite bus remote expansion method
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