Folding interpolation architecture ADC pre-amplification array circuit capable of calibrating output imbalance
The invention provides a folding interpolation architecture ADC pre-amplification array circuit capable of calibrating output imbalance. The circuit comprises a calibration logic control circuit, a benchmark reference voltage DAC, a calibration current steering DAC circuit and a pre-amplifier array...
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| creator | DONG HAI WANG ZONGMIN LEE HEE-TAEK ZHANG TIELIANG CHU FEI BING ZHAOHANG HUO MIAO YANG SONG YANG LONG XUE PEIFAN |
| description | The invention provides a folding interpolation architecture ADC pre-amplification array circuit capable of calibrating output imbalance. The circuit comprises a calibration logic control circuit, a benchmark reference voltage DAC, a calibration current steering DAC circuit and a pre-amplifier array circuit. The differential positive output end of each amplifier of the pre-amplifier array circuit is connected in parallel with a positive output end calibration resistor, and the negative output end of each amplifier is connected in parallel with a negative output end calibration resistor; the calibration logic control circuit is used for generating a reference voltage signal Vclt; n: 0gt; comparing Vclt caused by the reference voltage signal; n: 0gt; an output Vult of the ADC core; n: 0gt; and a reference voltage signal Vclt; n: 0gt; obtaining a calibration vector Dlt; n: 0gt; calibrating the vector Dlt; n: 0gt; converting into an offset calibration control code Q0lt; n: 0gt; -Qmlt,-Qmlt; n: 0gt; ; the calibrati |
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The circuit comprises a calibration logic control circuit, a benchmark reference voltage DAC, a calibration current steering DAC circuit and a pre-amplifier array circuit. The differential positive output end of each amplifier of the pre-amplifier array circuit is connected in parallel with a positive output end calibration resistor, and the negative output end of each amplifier is connected in parallel with a negative output end calibration resistor; the calibration logic control circuit is used for generating a reference voltage signal Vclt; n: 0gt; comparing Vclt caused by the reference voltage signal; n: 0gt; an output Vult of the ADC core; n: 0gt; and a reference voltage signal Vclt; n: 0gt; obtaining a calibration vector Dlt; n: 0gt; calibrating the vector Dlt; n: 0gt; converting into an offset calibration control code Q0lt; n: 0gt; -Qmlt,-Qmlt; n: 0gt; ; the calibrati</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | AMPLIFIERS BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY |
| title | Folding interpolation architecture ADC pre-amplification array circuit capable of calibrating output imbalance |
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