Topology reconstruction method based on flow perception in multi-core-particle interconnection network
The invention provides a topology reconstruction method based on flow perception in a multi-core-particle interconnection network. The multi-core-particle interconnection network topology comprises an in-core-particle network topology and an inter-core-particle network topology, a configurable cross...
Gespeichert in:
Hauptverfasser: | , , , , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | WANG XIAOHANG UE HIROAKI LI SHUNBIN DENG QINGWEN SUN TIANNING WAN ZHIQUAN WANG ZHIYU |
description | The invention provides a topology reconstruction method based on flow perception in a multi-core-particle interconnection network. The multi-core-particle interconnection network topology comprises an in-core-particle network topology and an inter-core-particle network topology, a configurable crossbar switch network is added in the inter-core-particle network, and the configurable crossbar switches are configured by using a heuristic reconstruction method, so that a directly connected virtual link is provided for routers which are in frequent communication, and the multi-core-particle interconnection network topology is realized. Therefore, the average hop count and the network delay are reduced. By reducing the number of core grain pins and reducing the average hop count and delay of a network, the area and cost of a chip are reduced, the performance of the chip is improved, and the method can be used for designing a universal processor and a special processor for various applications.
本发明提供了一种在多芯粒互连网络中基于流量 |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116260760A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116260760A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116260760A3</originalsourceid><addsrcrecordid>eNqNzEEKwjAQBdBuXIh6h3iAQKsQ11IUV666LzH90dCYCcmU4u0N6gFcDf__xywr21EkT_eXSDAUMqfJsKMgnuAHDeKmMwZRsvU0i4hkED-7K2Ty7KShBBl1Ymc8Ss3FUAj4vgngmdK4rhZW-4zN766q7fnUtReJSD1y1AZF9u21adRO1QdVH_f_mDcpiEDp</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Topology reconstruction method based on flow perception in multi-core-particle interconnection network</title><source>esp@cenet</source><creator>WANG XIAOHANG ; UE HIROAKI ; LI SHUNBIN ; DENG QINGWEN ; SUN TIANNING ; WAN ZHIQUAN ; WANG ZHIYU</creator><creatorcontrib>WANG XIAOHANG ; UE HIROAKI ; LI SHUNBIN ; DENG QINGWEN ; SUN TIANNING ; WAN ZHIQUAN ; WANG ZHIYU</creatorcontrib><description>The invention provides a topology reconstruction method based on flow perception in a multi-core-particle interconnection network. The multi-core-particle interconnection network topology comprises an in-core-particle network topology and an inter-core-particle network topology, a configurable crossbar switch network is added in the inter-core-particle network, and the configurable crossbar switches are configured by using a heuristic reconstruction method, so that a directly connected virtual link is provided for routers which are in frequent communication, and the multi-core-particle interconnection network topology is realized. Therefore, the average hop count and the network delay are reduced. By reducing the number of core grain pins and reducing the average hop count and delay of a network, the area and cost of a chip are reduced, the performance of the chip is improved, and the method can be used for designing a universal processor and a special processor for various applications.
本发明提供了一种在多芯粒互连网络中基于流量</description><language>chi ; eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230613&DB=EPODOC&CC=CN&NR=116260760A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230613&DB=EPODOC&CC=CN&NR=116260760A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WANG XIAOHANG</creatorcontrib><creatorcontrib>UE HIROAKI</creatorcontrib><creatorcontrib>LI SHUNBIN</creatorcontrib><creatorcontrib>DENG QINGWEN</creatorcontrib><creatorcontrib>SUN TIANNING</creatorcontrib><creatorcontrib>WAN ZHIQUAN</creatorcontrib><creatorcontrib>WANG ZHIYU</creatorcontrib><title>Topology reconstruction method based on flow perception in multi-core-particle interconnection network</title><description>The invention provides a topology reconstruction method based on flow perception in a multi-core-particle interconnection network. The multi-core-particle interconnection network topology comprises an in-core-particle network topology and an inter-core-particle network topology, a configurable crossbar switch network is added in the inter-core-particle network, and the configurable crossbar switches are configured by using a heuristic reconstruction method, so that a directly connected virtual link is provided for routers which are in frequent communication, and the multi-core-particle interconnection network topology is realized. Therefore, the average hop count and the network delay are reduced. By reducing the number of core grain pins and reducing the average hop count and delay of a network, the area and cost of a chip are reduced, the performance of the chip is improved, and the method can be used for designing a universal processor and a special processor for various applications.
本发明提供了一种在多芯粒互连网络中基于流量</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzEEKwjAQBdBuXIh6h3iAQKsQ11IUV666LzH90dCYCcmU4u0N6gFcDf__xywr21EkT_eXSDAUMqfJsKMgnuAHDeKmMwZRsvU0i4hkED-7K2Ty7KShBBl1Ymc8Ss3FUAj4vgngmdK4rhZW-4zN766q7fnUtReJSD1y1AZF9u21adRO1QdVH_f_mDcpiEDp</recordid><startdate>20230613</startdate><enddate>20230613</enddate><creator>WANG XIAOHANG</creator><creator>UE HIROAKI</creator><creator>LI SHUNBIN</creator><creator>DENG QINGWEN</creator><creator>SUN TIANNING</creator><creator>WAN ZHIQUAN</creator><creator>WANG ZHIYU</creator><scope>EVB</scope></search><sort><creationdate>20230613</creationdate><title>Topology reconstruction method based on flow perception in multi-core-particle interconnection network</title><author>WANG XIAOHANG ; UE HIROAKI ; LI SHUNBIN ; DENG QINGWEN ; SUN TIANNING ; WAN ZHIQUAN ; WANG ZHIYU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116260760A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>WANG XIAOHANG</creatorcontrib><creatorcontrib>UE HIROAKI</creatorcontrib><creatorcontrib>LI SHUNBIN</creatorcontrib><creatorcontrib>DENG QINGWEN</creatorcontrib><creatorcontrib>SUN TIANNING</creatorcontrib><creatorcontrib>WAN ZHIQUAN</creatorcontrib><creatorcontrib>WANG ZHIYU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WANG XIAOHANG</au><au>UE HIROAKI</au><au>LI SHUNBIN</au><au>DENG QINGWEN</au><au>SUN TIANNING</au><au>WAN ZHIQUAN</au><au>WANG ZHIYU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Topology reconstruction method based on flow perception in multi-core-particle interconnection network</title><date>2023-06-13</date><risdate>2023</risdate><abstract>The invention provides a topology reconstruction method based on flow perception in a multi-core-particle interconnection network. The multi-core-particle interconnection network topology comprises an in-core-particle network topology and an inter-core-particle network topology, a configurable crossbar switch network is added in the inter-core-particle network, and the configurable crossbar switches are configured by using a heuristic reconstruction method, so that a directly connected virtual link is provided for routers which are in frequent communication, and the multi-core-particle interconnection network topology is realized. Therefore, the average hop count and the network delay are reduced. By reducing the number of core grain pins and reducing the average hop count and delay of a network, the area and cost of a chip are reduced, the performance of the chip is improved, and the method can be used for designing a universal processor and a special processor for various applications.
本发明提供了一种在多芯粒互连网络中基于流量</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN116260760A |
source | esp@cenet |
subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | Topology reconstruction method based on flow perception in multi-core-particle interconnection network |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T00%3A05%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WANG%20XIAOHANG&rft.date=2023-06-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN116260760A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |