LVDS (Low Voltage Differential Signaling) pre-emphasis clock driving circuit with capacitor

The invention relates to an LVDS (Low Voltage Differential Signaling) pre-emphasis clock driving circuit with a capacitor, and belongs to the field of microcircuit structures. The circuit comprises an LVDS (Low Voltage Differential Signaling) main body signal structure path and a pre-emphasis signal path, wherein a capacitor is added in the pre-emphasis signal path. An input signal of the LVDS main body path is connected with an input signal of the pre-emphasis path, and an output signal of the LVDS main body path is connected with an output signal of the pre-emphasis path. The invention has the advantages of simple structure, high efficiency and low power consumption. 本发明涉及一种带有电容的LVDS预加重时钟驱动电路，属于微电路结构领域。本发明包括LVDS主体信号结构通路和预加重信号通路，其中预加重信号通路中增加电容。LVDS主体通路的输入信号同预加重通路的输入信号相连接，同样LVDS主体通路的输出信号同预加重通路的输出信号相连接。本发明具有结构简单、效率高、功耗较低的优点。