Integrated chip structure and forming method thereof
The invention relates to an integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. And a bottom electrode via surrounded by one or more inner sidewalls of the lower insulat...
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| creator | KUANG XUNCHONG GUAN ZHENYU FU SHENGWEN |
| description | The invention relates to an integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. And a bottom electrode via surrounded by one or more inner sidewalls of the lower insulating structure. The bottom electrode via includes a barrier surrounding the conductive core. A bottom electrode is disposed on the bottom electrode via, a data storage structure over the bottom electrode, and a top electrode over the data storage structure. The barrier is a sidewall disposed along one or more inner sidewalls of the lower insulating structure and a horizontal cover section projecting outwardly from the sidewall above a top surface of the lower insulating structure. The embodiment of the invention also provides a method for forming the integrated chip structure.
本发明涉及集成芯片结构。该集成芯片结构包括设置在围绕一个或多个下部互连件的下部介电结构上方的下部绝缘结构。由下部绝缘结构的一个或多个内侧壁围绕的底部电极通孔。底部电极通孔包括围绕导电芯的阻挡件。底部电极布置在底部电极通孔上，数据存储结构位于底部电极上方，以及顶部电极位于数据存储结构 |
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本发明涉及集成芯片结构。该集成芯片结构包括设置在围绕一个或多个下部互连件的下部介电结构上方的下部绝缘结构。由下部绝缘结构的一个或多个内侧壁围绕的底部电极通孔。底部电极通孔包括围绕导电芯的阻挡件。底部电极布置在底部电极通孔上，数据存储结构位于底部电极上方，以及顶部电极位于数据存储结构</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230523&DB=EPODOC&CC=CN&NR=116153857A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230523&DB=EPODOC&CC=CN&NR=116153857A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KUANG XUNCHONG</creatorcontrib><creatorcontrib>GUAN ZHENYU</creatorcontrib><creatorcontrib>FU SHENGWEN</creatorcontrib><title>Integrated chip structure and forming method thereof</title><description>The invention relates to an integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. And a bottom electrode via surrounded by one or more inner sidewalls of the lower insulating structure. The bottom electrode via includes a barrier surrounding the conductive core. A bottom electrode is disposed on the bottom electrode via, a data storage structure over the bottom electrode, and a top electrode over the data storage structure. The barrier is a sidewall disposed along one or more inner sidewalls of the lower insulating structure and a horizontal cover section projecting outwardly from the sidewall above a top surface of the lower insulating structure. The embodiment of the invention also provides a method for forming the integrated chip structure.
本发明涉及集成芯片结构。该集成芯片结构包括设置在围绕一个或多个下部互连件的下部介电结构上方的下部绝缘结构。由下部绝缘结构的一个或多个内侧壁围绕的底部电极通孔。底部电极通孔包括围绕导电芯的阻挡件。底部电极布置在底部电极通孔上，数据存储结构位于底部电极上方，以及顶部电极位于数据存储结构</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDxzCtJTS9KLElNUUjOyCxQKC4pKk0uKS1KVUjMS1FIyy_KzcxLV8hNLcnIT1EoyUgtSs1P42FgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoZmhqbGFqbmjsbEqAEAUGYtFA</recordid><startdate>20230523</startdate><enddate>20230523</enddate><creator>KUANG XUNCHONG</creator><creator>GUAN ZHENYU</creator><creator>FU SHENGWEN</creator><scope>EVB</scope></search><sort><creationdate>20230523</creationdate><title>Integrated chip structure and forming method thereof</title><author>KUANG XUNCHONG ; GUAN ZHENYU ; FU SHENGWEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116153857A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KUANG XUNCHONG</creatorcontrib><creatorcontrib>GUAN ZHENYU</creatorcontrib><creatorcontrib>FU SHENGWEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KUANG XUNCHONG</au><au>GUAN ZHENYU</au><au>FU SHENGWEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated chip structure and forming method thereof</title><date>2023-05-23</date><risdate>2023</risdate><abstract>The invention relates to an integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. And a bottom electrode via surrounded by one or more inner sidewalls of the lower insulating structure. The bottom electrode via includes a barrier surrounding the conductive core. A bottom electrode is disposed on the bottom electrode via, a data storage structure over the bottom electrode, and a top electrode over the data storage structure. The barrier is a sidewall disposed along one or more inner sidewalls of the lower insulating structure and a horizontal cover section projecting outwardly from the sidewall above a top surface of the lower insulating structure. The embodiment of the invention also provides a method for forming the integrated chip structure.
本发明涉及集成芯片结构。该集成芯片结构包括设置在围绕一个或多个下部互连件的下部介电结构上方的下部绝缘结构。由下部绝缘结构的一个或多个内侧壁围绕的底部电极通孔。底部电极通孔包括围绕导电芯的阻挡件。底部电极布置在底部电极通孔上，数据存储结构位于底部电极上方，以及顶部电极位于数据存储结构</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Integrated chip structure and forming method thereof |
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