FPGA-based low-speed source synchronous data bit alignment correction method

The embodiment of the invention discloses a low-speed source synchronous data bit alignment correction method based on an FPGA (Field Programmable Gate Array). The method comprises the following steps: setting a clock line delay order and a data line delay order of a first channel; receiving an externally input serial training sequence, and performing serial-to-parallel conversion to obtain parallel data; acquiring a rising edge of the parallel data change and calculating parallel data during two data edge changes later; adjusting the total delay order to trigger the first data edge bounce, and recording the total delay order d1 when the first data edge bounce is triggered; adjusting the total delay order to trigger the second data edge bounce, and recording the total delay order d2 when the second data edge bounce is triggered; calculating the optimal total delay order D1 of the current channel, wherein D1 = (d1 + d2)/2; repeating the steps to complete the alignment correction of the other three channels and