Partitioned floating-point number parallelization additive operation method

Partitioned floating-point number parallelization additive operation method

The invention discloses a partitioning floating-point number parallelization additive operation method, which comprises the following steps of: designing a partitioning low-precision storage mode based on an IEEE754 floating-point number representation mode, partitioning a mantissa part of a floatin...

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Hauptverfasser: MIAO JIEHAO, BAI JIZHOU, BAO KAIXUAN, LI JINGRUI, HUANG BINGBIN, XU WEI
Format: Patent
Sprache:chi ; eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator MIAO JIEHAO
BAI JIZHOU
BAO KAIXUAN
LI JINGRUI
HUANG BINGBIN
XU WEI
description The invention discloses a partitioning floating-point number parallelization additive operation method, which comprises the following steps of: designing a partitioning low-precision storage mode based on an IEEE754 floating-point number representation mode, partitioning a mantissa part of a floating-point number by customizing a floating block digit, and partitioning the mantissa part of the floating-point number by utilizing the characteristic that an FPGA (Field Programmable Gate Array) can perform parallel processing. In the mantissa summation process, the floating blocks in all the lists of the addend storage pool are subjected to additive operation at the same time, and therefore the effect of improving the calculation efficiency is achieved. The method is simple to implement, can effectively reduce the calculation complexity, reduce the time delay generated by calculation and greatly improve the calculation efficiency under the condition that the calculation error is basically unchanged, and can adjust
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Partitioned floating-point number parallelization additive operation method
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