Semiconductor integrated device and manufacturing method thereof

The invention discloses a semiconductor integrated device and a manufacturing method thereof, and belongs to the technical field of semiconductors, and the semiconductor integrated device comprises a substrate which comprises a flash memory region, a first region and a second region; the plurality o...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LIN ZIREN, ZHANG ERDONG, YANG ZHIQIANG, LAI GUOWEN, XU ZHENGHONG
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator LIN ZIREN
ZHANG ERDONG
YANG ZHIQIANG
LAI GUOWEN
XU ZHENGHONG
description The invention discloses a semiconductor integrated device and a manufacturing method thereof, and belongs to the technical field of semiconductors, and the semiconductor integrated device comprises a substrate which comprises a flash memory region, a first region and a second region; the plurality of well regions are arranged in the substrate; the gate oxide layer is arranged on the well region; the first gate structure is arranged on the gate oxide layer on the flash memory region and the first region, the first gate structure comprises a first gate layer, an insulating layer and a second gate layer, and the insulating layer is arranged between the first gate layer and the second gate layer; the second gate structure is arranged on the gate oxide layer on the second region, and the second gate structure comprises the second gate layer; and the heavily doped region is positioned in the well region at the two sides of the first gate structure and the second gate structure. According to the semiconductor integr
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116053274A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116053274A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116053274A3</originalsourceid><addsrcrecordid>eNrjZHAITs3NTM7PSylNLskvUsjMK0lNL0osSU1RSEkty0xOVUjMS1HITcwrTUtMLiktysxLV8hNLcnIT1EoyUgtSs1P42FgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoZmBqbGRuYmjsbEqAEAHWkx7A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor integrated device and manufacturing method thereof</title><source>esp@cenet</source><creator>LIN ZIREN ; ZHANG ERDONG ; YANG ZHIQIANG ; LAI GUOWEN ; XU ZHENGHONG</creator><creatorcontrib>LIN ZIREN ; ZHANG ERDONG ; YANG ZHIQIANG ; LAI GUOWEN ; XU ZHENGHONG</creatorcontrib><description>The invention discloses a semiconductor integrated device and a manufacturing method thereof, and belongs to the technical field of semiconductors, and the semiconductor integrated device comprises a substrate which comprises a flash memory region, a first region and a second region; the plurality of well regions are arranged in the substrate; the gate oxide layer is arranged on the well region; the first gate structure is arranged on the gate oxide layer on the flash memory region and the first region, the first gate structure comprises a first gate layer, an insulating layer and a second gate layer, and the insulating layer is arranged between the first gate layer and the second gate layer; the second gate structure is arranged on the gate oxide layer on the second region, and the second gate structure comprises the second gate layer; and the heavily doped region is positioned in the well region at the two sides of the first gate structure and the second gate structure. According to the semiconductor integr</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230502&amp;DB=EPODOC&amp;CC=CN&amp;NR=116053274A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230502&amp;DB=EPODOC&amp;CC=CN&amp;NR=116053274A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIN ZIREN</creatorcontrib><creatorcontrib>ZHANG ERDONG</creatorcontrib><creatorcontrib>YANG ZHIQIANG</creatorcontrib><creatorcontrib>LAI GUOWEN</creatorcontrib><creatorcontrib>XU ZHENGHONG</creatorcontrib><title>Semiconductor integrated device and manufacturing method thereof</title><description>The invention discloses a semiconductor integrated device and a manufacturing method thereof, and belongs to the technical field of semiconductors, and the semiconductor integrated device comprises a substrate which comprises a flash memory region, a first region and a second region; the plurality of well regions are arranged in the substrate; the gate oxide layer is arranged on the well region; the first gate structure is arranged on the gate oxide layer on the flash memory region and the first region, the first gate structure comprises a first gate layer, an insulating layer and a second gate layer, and the insulating layer is arranged between the first gate layer and the second gate layer; the second gate structure is arranged on the gate oxide layer on the second region, and the second gate structure comprises the second gate layer; and the heavily doped region is positioned in the well region at the two sides of the first gate structure and the second gate structure. According to the semiconductor integr</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAITs3NTM7PSylNLskvUsjMK0lNL0osSU1RSEkty0xOVUjMS1HITcwrTUtMLiktysxLV8hNLcnIT1EoyUgtSs1P42FgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoZmBqbGRuYmjsbEqAEAHWkx7A</recordid><startdate>20230502</startdate><enddate>20230502</enddate><creator>LIN ZIREN</creator><creator>ZHANG ERDONG</creator><creator>YANG ZHIQIANG</creator><creator>LAI GUOWEN</creator><creator>XU ZHENGHONG</creator><scope>EVB</scope></search><sort><creationdate>20230502</creationdate><title>Semiconductor integrated device and manufacturing method thereof</title><author>LIN ZIREN ; ZHANG ERDONG ; YANG ZHIQIANG ; LAI GUOWEN ; XU ZHENGHONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116053274A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LIN ZIREN</creatorcontrib><creatorcontrib>ZHANG ERDONG</creatorcontrib><creatorcontrib>YANG ZHIQIANG</creatorcontrib><creatorcontrib>LAI GUOWEN</creatorcontrib><creatorcontrib>XU ZHENGHONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIN ZIREN</au><au>ZHANG ERDONG</au><au>YANG ZHIQIANG</au><au>LAI GUOWEN</au><au>XU ZHENGHONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor integrated device and manufacturing method thereof</title><date>2023-05-02</date><risdate>2023</risdate><abstract>The invention discloses a semiconductor integrated device and a manufacturing method thereof, and belongs to the technical field of semiconductors, and the semiconductor integrated device comprises a substrate which comprises a flash memory region, a first region and a second region; the plurality of well regions are arranged in the substrate; the gate oxide layer is arranged on the well region; the first gate structure is arranged on the gate oxide layer on the flash memory region and the first region, the first gate structure comprises a first gate layer, an insulating layer and a second gate layer, and the insulating layer is arranged between the first gate layer and the second gate layer; the second gate structure is arranged on the gate oxide layer on the second region, and the second gate structure comprises the second gate layer; and the heavily doped region is positioned in the well region at the two sides of the first gate structure and the second gate structure. According to the semiconductor integr</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN116053274A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor integrated device and manufacturing method thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T17%3A14%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LIN%20ZIREN&rft.date=2023-05-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN116053274A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true