Frequency multiplier circuit with adjustable output pulse width and chip

The invention discloses a frequency multiplier circuit with adjustable output pulse width and a chip, the frequency multiplier circuit comprises a buffer, a delay adjustable frequency division unit and a logic circuit, the input end of the buffer is used for receiving an input signal, and the first output end and the second output end of the buffer are used for outputting a group of differential clock signals; the input end of the delay adjustable frequency division unit is used for receiving a frequency multiplication signal output by the frequency multiplication circuit, and the first output end and the second output end of the delay adjustable frequency division unit are used for outputting another group of differential clock signals; the input end of the logic circuit is used for receiving two groups of differential clock signals, and the output end of the logic circuit outputs frequency multiplication signals based on logical operation of the two groups of differential clock signals. According to the fre