Processor instruction processing device and method supporting compression instruction

The invention provides a processor instruction processing device and method supporting instruction compression, and the device comprises a program counter, a first instruction memory, a second instruction memory, a comparison module, an instruction length unification module, a pre-decoding module and a processing module. A storage array of N paths of buffer instructions and instruction labels corresponding to the storage array are read and stored through a program counter, and a comparison module determines whether the instruction labels of the N paths of buffer instructions are hit or not so as to select a corresponding hit path buffer instruction when the instruction labels are hit. And expanding the storage array hitting the path buffer instruction into a standard instruction with a uniform length through an instruction length unifying module, pre-decoding the standard instruction through a pre-decoding module, and carrying out pipeline-level processing on uniform coding information obtained through pre-de