Through glass core via pitch with bump pitch scale to achieve substrate count reduction
The present disclosure relates to through glass core via pitch for bump pitch scale to achieve substrate count reduction. Embodiments disclosed herein include an electronic package. In an embodiment, an electronic package includes a package substrate, where the package substrate includes a core subs...
Gespeichert in:
Hauptverfasser: | , , , , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | The present disclosure relates to through glass core via pitch for bump pitch scale to achieve substrate count reduction. Embodiments disclosed herein include an electronic package. In an embodiment, an electronic package includes a package substrate, where the package substrate includes a core substrate. In an embodiment, the core substrate includes glass. In an embodiment, a via passes through the core substrate. In an embodiment, a die is coupled to a package substrate, where the die includes an IO interface. In an embodiment, the IO interface is electrically coupled to the via, and the via is within the footprint of the die.
本公开内容涉及利用凸块间距尺度的穿玻璃芯过孔间距来实现衬底层数减少。本文公开的实施例包括电子封装。在实施例中,一种电子封装包括封装衬底,其中封装衬底包括:芯衬底。在实施例中,芯衬底包括玻璃。在实施例中,过孔穿过所述芯衬底。在实施例中,管芯耦接到封装衬底,其中,管芯包括IO接口。在实施例中,IO接口电耦接到过孔,并且过孔在管芯的占有面积之内。 |
---|