Neuromorphic data processing system based on SPI bus

The invention relates to the technical field of integrated circuits and neural networks, in particular to a neuromorphic data processing system based on an SPI (Serial Peripheral Interface) bus. According to the neuromorphic data processing system based on the SPI bus, cooperative work of multiple i...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: ZHANG XIAOYANG, HU SHAOGANG, LIU QIANG, ZHOU PUJUN, QIAO GUANCHAO
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator ZHANG XIAOYANG
HU SHAOGANG
LIU QIANG
ZHOU PUJUN
QIAO GUANCHAO
description The invention relates to the technical field of integrated circuits and neural networks, in particular to a neuromorphic data processing system based on an SPI (Serial Peripheral Interface) bus. According to the neuromorphic data processing system based on the SPI bus, cooperative work of multiple internal architectures is achieved through the SPI protocol with the adjustable data bit width, compact design is adopted, neuron parameters are stored out of a chip, the overhead and power consumption of on-chip storage are effectively reduced, and the system has the advantages of being simple in structure and convenient to use. Rich instruction packets and highly flexible and configurable neurons are designed for the architecture, the configuration of the network-on-chip can be easily completed, a large amount of register overhead in the network-on-chip is effectively reduced by adopting a register multiplexing technology, a router is used for transmitting information between cores, and the reliability of data is
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN115860082A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN115860082A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN115860082A3</originalsourceid><addsrcrecordid>eNrjZDDxSy0tys_NLyrIyExWSEksSVQoKMpPTi0uzsxLVyiuLC5JzVVISixOTVHIz1MIDvBUSCot5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoamFmYGBhZGjsbEqAEAJjgsgg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Neuromorphic data processing system based on SPI bus</title><source>esp@cenet</source><creator>ZHANG XIAOYANG ; HU SHAOGANG ; LIU QIANG ; ZHOU PUJUN ; QIAO GUANCHAO</creator><creatorcontrib>ZHANG XIAOYANG ; HU SHAOGANG ; LIU QIANG ; ZHOU PUJUN ; QIAO GUANCHAO</creatorcontrib><description>The invention relates to the technical field of integrated circuits and neural networks, in particular to a neuromorphic data processing system based on an SPI (Serial Peripheral Interface) bus. According to the neuromorphic data processing system based on the SPI bus, cooperative work of multiple internal architectures is achieved through the SPI protocol with the adjustable data bit width, compact design is adopted, neuron parameters are stored out of a chip, the overhead and power consumption of on-chip storage are effectively reduced, and the system has the advantages of being simple in structure and convenient to use. Rich instruction packets and highly flexible and configurable neurons are designed for the architecture, the configuration of the network-on-chip can be easily completed, a large amount of register overhead in the network-on-chip is effectively reduced by adopting a register multiplexing technology, a router is used for transmitting information between cores, and the reliability of data is</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230328&amp;DB=EPODOC&amp;CC=CN&amp;NR=115860082A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230328&amp;DB=EPODOC&amp;CC=CN&amp;NR=115860082A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZHANG XIAOYANG</creatorcontrib><creatorcontrib>HU SHAOGANG</creatorcontrib><creatorcontrib>LIU QIANG</creatorcontrib><creatorcontrib>ZHOU PUJUN</creatorcontrib><creatorcontrib>QIAO GUANCHAO</creatorcontrib><title>Neuromorphic data processing system based on SPI bus</title><description>The invention relates to the technical field of integrated circuits and neural networks, in particular to a neuromorphic data processing system based on an SPI (Serial Peripheral Interface) bus. According to the neuromorphic data processing system based on the SPI bus, cooperative work of multiple internal architectures is achieved through the SPI protocol with the adjustable data bit width, compact design is adopted, neuron parameters are stored out of a chip, the overhead and power consumption of on-chip storage are effectively reduced, and the system has the advantages of being simple in structure and convenient to use. Rich instruction packets and highly flexible and configurable neurons are designed for the architecture, the configuration of the network-on-chip can be easily completed, a large amount of register overhead in the network-on-chip is effectively reduced by adopting a register multiplexing technology, a router is used for transmitting information between cores, and the reliability of data is</description><subject>CALCULATING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDxSy0tys_NLyrIyExWSEksSVQoKMpPTi0uzsxLVyiuLC5JzVVISixOTVHIz1MIDvBUSCot5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoamFmYGBhZGjsbEqAEAJjgsgg</recordid><startdate>20230328</startdate><enddate>20230328</enddate><creator>ZHANG XIAOYANG</creator><creator>HU SHAOGANG</creator><creator>LIU QIANG</creator><creator>ZHOU PUJUN</creator><creator>QIAO GUANCHAO</creator><scope>EVB</scope></search><sort><creationdate>20230328</creationdate><title>Neuromorphic data processing system based on SPI bus</title><author>ZHANG XIAOYANG ; HU SHAOGANG ; LIU QIANG ; ZHOU PUJUN ; QIAO GUANCHAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115860082A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>ZHANG XIAOYANG</creatorcontrib><creatorcontrib>HU SHAOGANG</creatorcontrib><creatorcontrib>LIU QIANG</creatorcontrib><creatorcontrib>ZHOU PUJUN</creatorcontrib><creatorcontrib>QIAO GUANCHAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZHANG XIAOYANG</au><au>HU SHAOGANG</au><au>LIU QIANG</au><au>ZHOU PUJUN</au><au>QIAO GUANCHAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Neuromorphic data processing system based on SPI bus</title><date>2023-03-28</date><risdate>2023</risdate><abstract>The invention relates to the technical field of integrated circuits and neural networks, in particular to a neuromorphic data processing system based on an SPI (Serial Peripheral Interface) bus. According to the neuromorphic data processing system based on the SPI bus, cooperative work of multiple internal architectures is achieved through the SPI protocol with the adjustable data bit width, compact design is adopted, neuron parameters are stored out of a chip, the overhead and power consumption of on-chip storage are effectively reduced, and the system has the advantages of being simple in structure and convenient to use. Rich instruction packets and highly flexible and configurable neurons are designed for the architecture, the configuration of the network-on-chip can be easily completed, a large amount of register overhead in the network-on-chip is effectively reduced by adopting a register multiplexing technology, a router is used for transmitting information between cores, and the reliability of data is</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN115860082A
source esp@cenet
subjects CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Neuromorphic data processing system based on SPI bus
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T11%3A55%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ZHANG%20XIAOYANG&rft.date=2023-03-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN115860082A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true