Efficient lightweight NTT multiplier circuit based on lattice cipher

Efficient lightweight NTT multiplier circuit based on lattice cipher

The invention discloses an efficient lightweight NTT multiplier circuit based on a lattice password. The efficient lightweight NTT multiplier circuit comprises an NTT control unit, a dual-port RAM (Random Access Memory) and two parallel NTT butterfly computing units, wherein the modes of the NTT but...

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Hauptverfasser: NI ZIYING, CUI YIJUN, LIU DONGSHENG, XU TIANYU, WANG CHENGHUA, LIU WEIQIANG, YU SHICHAO
Format: Patent
Sprache:chi ; eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator NI ZIYING
CUI YIJUN
LIU DONGSHENG
XU TIANYU
WANG CHENGHUA
LIU WEIQIANG
YU SHICHAO
description The invention discloses an efficient lightweight NTT multiplier circuit based on a lattice password. The efficient lightweight NTT multiplier circuit comprises an NTT control unit, a dual-port RAM (Random Access Memory) and two parallel NTT butterfly computing units, wherein the modes of the NTT butterfly computing units can be switched, the NTT control unit is connected with the dual-port RAM, and the dual-port RAM is respectively connected with the two parallel NTT butterfly computing units; data are input into the NTT butterfly calculation unit through the dual-port RAM, different NTT butterfly calculation unit modes are selected through mode control signals of the NTT control unit, the NTT butterfly calculation unit processes the data, multiplication results obtained through calculation are reduced through the Barrett reduction unit, and then the multiplication results are written back into the dual-port RAM according to the specific sequence of the NTT algorithm. The calculation complexity and the hardwa
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The efficient lightweight NTT multiplier circuit comprises an NTT control unit, a dual-port RAM (Random Access Memory) and two parallel NTT butterfly computing units, wherein the modes of the NTT butterfly computing units can be switched, the NTT control unit is connected with the dual-port RAM, and the dual-port RAM is respectively connected with the two parallel NTT butterfly computing units; data are input into the NTT butterfly calculation unit through the dual-port RAM, different NTT butterfly calculation unit modes are selected through mode control signals of the NTT control unit, the NTT butterfly calculation unit processes the data, multiplication results obtained through calculation are reduced through the Barrett reduction unit, and then the multiplication results are written back into the dual-port RAM according to the specific sequence of the NTT algorithm. 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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Efficient lightweight NTT multiplier circuit based on lattice cipher
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