Semiconductor layout pattern and forming method thereof
The invention discloses a semiconductor layout pattern and a forming method thereof, the semiconductor layout pattern comprises a substrate, a plurality of ternary content addressable memories (TCAMs) are arranged on the substrate, the layout of at least two TCAMs is in mirror symmetry along an axis...
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| creator | GUO YOUCE HUANG LIPING YU XINCHI WANG SHURU ZENG JUNYAN ZHUANG MENGPING HUANG JUNXIAN |
| description | The invention discloses a semiconductor layout pattern and a forming method thereof, the semiconductor layout pattern comprises a substrate, a plurality of ternary content addressable memories (TCAMs) are arranged on the substrate, the layout of at least two TCAMs is in mirror symmetry along an axis of symmetry, and the two TCAMs are commonly connected to the same search line (SL).
本发明公开一种半导体布局图案及其形成方法，其中该半导体布局图案包含一基底，基底上有多个三元内容可定址存储器(Ternary contentaddressable memory,TCAM)，其中至少两个TCAM的布局沿着一对称轴相互镜射对称，且该两个TCAM共同连接到同一搜寻线(SL)。 |
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本发明公开一种半导体布局图案及其形成方法，其中该半导体布局图案包含一基底，基底上有多个三元内容可定址存储器(Ternary contentaddressable memory,TCAM)，其中至少两个TCAM的布局沿着一对称轴相互镜射对称，且该两个TCAM共同连接到同一搜寻线(SL)。</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230110&DB=EPODOC&CC=CN&NR=115588666A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230110&DB=EPODOC&CC=CN&NR=115588666A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GUO YOUCE</creatorcontrib><creatorcontrib>HUANG LIPING</creatorcontrib><creatorcontrib>YU XINCHI</creatorcontrib><creatorcontrib>WANG SHURU</creatorcontrib><creatorcontrib>ZENG JUNYAN</creatorcontrib><creatorcontrib>ZHUANG MENGPING</creatorcontrib><creatorcontrib>HUANG JUNXIAN</creatorcontrib><title>Semiconductor layout pattern and forming method thereof</title><description>The invention discloses a semiconductor layout pattern and a forming method thereof, the semiconductor layout pattern comprises a substrate, a plurality of ternary content addressable memories (TCAMs) are arranged on the substrate, the layout of at least two TCAMs is in mirror symmetry along an axis of symmetry, and the two TCAMs are commonly connected to the same search line (SL).
本发明公开一种半导体布局图案及其形成方法，其中该半导体布局图案包含一基底，基底上有多个三元内容可定址存储器(Ternary contentaddressable memory,TCAM)，其中至少两个TCAM的布局沿着一对称轴相互镜射对称，且该两个TCAM共同连接到同一搜寻线(SL)。</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAPTs3NTM7PSylNLskvUshJrMwvLVEoSCwpSS3KU0jMS1FIyy_KzcxLV8hNLcnIT1EoyUgtSs1P42FgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoamphYWZmZmjsbEqAEAFnIuiA</recordid><startdate>20230110</startdate><enddate>20230110</enddate><creator>GUO YOUCE</creator><creator>HUANG LIPING</creator><creator>YU XINCHI</creator><creator>WANG SHURU</creator><creator>ZENG JUNYAN</creator><creator>ZHUANG MENGPING</creator><creator>HUANG JUNXIAN</creator><scope>EVB</scope></search><sort><creationdate>20230110</creationdate><title>Semiconductor layout pattern and forming method thereof</title><author>GUO YOUCE ; HUANG LIPING ; YU XINCHI ; WANG SHURU ; ZENG JUNYAN ; ZHUANG MENGPING ; HUANG JUNXIAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115588666A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GUO YOUCE</creatorcontrib><creatorcontrib>HUANG LIPING</creatorcontrib><creatorcontrib>YU XINCHI</creatorcontrib><creatorcontrib>WANG SHURU</creatorcontrib><creatorcontrib>ZENG JUNYAN</creatorcontrib><creatorcontrib>ZHUANG MENGPING</creatorcontrib><creatorcontrib>HUANG JUNXIAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GUO YOUCE</au><au>HUANG LIPING</au><au>YU XINCHI</au><au>WANG SHURU</au><au>ZENG JUNYAN</au><au>ZHUANG MENGPING</au><au>HUANG JUNXIAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor layout pattern and forming method thereof</title><date>2023-01-10</date><risdate>2023</risdate><abstract>The invention discloses a semiconductor layout pattern and a forming method thereof, the semiconductor layout pattern comprises a substrate, a plurality of ternary content addressable memories (TCAMs) are arranged on the substrate, the layout of at least two TCAMs is in mirror symmetry along an axis of symmetry, and the two TCAMs are commonly connected to the same search line (SL).
本发明公开一种半导体布局图案及其形成方法，其中该半导体布局图案包含一基底，基底上有多个三元内容可定址存储器(Ternary contentaddressable memory,TCAM)，其中至少两个TCAM的布局沿着一对称轴相互镜射对称，且该两个TCAM共同连接到同一搜寻线(SL)。</abstract><oa>free_for_read</oa></addata></record> |
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| title | Semiconductor layout pattern and forming method thereof |
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