Network and edge acceleration tile (NEXT) architecture

Examples described herein include a system including a processing unit package including at least one core and at least one load transfer processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one load transfer processing devic...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHILIKIN ANDREY, RAKAKULA, NAVEEN, MOSUR, LOKPRAVEEN, FLEMING PATRICK, MCDONALD NEIL D, GANGA, ELANGO, S, IYER, VENKATESH, KRISHNA, COUCH PATRICK G, KEATING BRIAN A
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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