Array substrate, preparation method thereof and display panel

The invention provides an array substrate, a preparation method thereof and a display panel, a thin film transistor is arranged in the array substrate, and the array substrate comprises a substrate; the first conducting layer is arranged on the substrate and comprises a first electrode and a virtual...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: JIANG ZHIXIONG, HUANG JIAHUI, CAI ZHIHUI, GONG CHENG, YU MINGJUE, WANG QIANG
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator JIANG ZHIXIONG
HUANG JIAHUI
CAI ZHIHUI
GONG CHENG
YU MINGJUE
WANG QIANG
description The invention provides an array substrate, a preparation method thereof and a display panel, a thin film transistor is arranged in the array substrate, and the array substrate comprises a substrate; the first conducting layer is arranged on the substrate and comprises a first electrode and a virtual electrode, and the first electrode and the virtual electrode are arranged at an interval; the second conducting layer is arranged on the first conducting layer and comprises a grid electrode of the thin film transistor, the grid electrode and the virtual electrode are arranged in a stacked mode, and in the material of the first conducting layer, the molar percentage of tin element is smaller than 1%; wherein the material of the first conductive layer comprises a lanthanide metal oxide, and the molar percentage of the lanthanide element is 1%-5%; and/or the material of the first conductive layer comprises indium metal oxide, and the molar percentage of the indium element is 30%-50%. The problem that etching is not
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN115312546A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN115312546A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN115312546A3</originalsourceid><addsrcrecordid>eNrjZLB1LCpKrFQoLk0qLilKLEnVUSgoSi1IBDIz8_MUclNLMvJTFEoyUotS89MUEvNSFFIyiwtygDoKEvNSc3gYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSbyzn6GhqbGhkamJmaMxMWoAOBcwUA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Array substrate, preparation method thereof and display panel</title><source>esp@cenet</source><creator>JIANG ZHIXIONG ; HUANG JIAHUI ; CAI ZHIHUI ; GONG CHENG ; YU MINGJUE ; WANG QIANG</creator><creatorcontrib>JIANG ZHIXIONG ; HUANG JIAHUI ; CAI ZHIHUI ; GONG CHENG ; YU MINGJUE ; WANG QIANG</creatorcontrib><description>The invention provides an array substrate, a preparation method thereof and a display panel, a thin film transistor is arranged in the array substrate, and the array substrate comprises a substrate; the first conducting layer is arranged on the substrate and comprises a first electrode and a virtual electrode, and the first electrode and the virtual electrode are arranged at an interval; the second conducting layer is arranged on the first conducting layer and comprises a grid electrode of the thin film transistor, the grid electrode and the virtual electrode are arranged in a stacked mode, and in the material of the first conducting layer, the molar percentage of tin element is smaller than 1%; wherein the material of the first conductive layer comprises a lanthanide metal oxide, and the molar percentage of the lanthanide element is 1%-5%; and/or the material of the first conductive layer comprises indium metal oxide, and the molar percentage of the indium element is 30%-50%. The problem that etching is not</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221108&amp;DB=EPODOC&amp;CC=CN&amp;NR=115312546A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221108&amp;DB=EPODOC&amp;CC=CN&amp;NR=115312546A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JIANG ZHIXIONG</creatorcontrib><creatorcontrib>HUANG JIAHUI</creatorcontrib><creatorcontrib>CAI ZHIHUI</creatorcontrib><creatorcontrib>GONG CHENG</creatorcontrib><creatorcontrib>YU MINGJUE</creatorcontrib><creatorcontrib>WANG QIANG</creatorcontrib><title>Array substrate, preparation method thereof and display panel</title><description>The invention provides an array substrate, a preparation method thereof and a display panel, a thin film transistor is arranged in the array substrate, and the array substrate comprises a substrate; the first conducting layer is arranged on the substrate and comprises a first electrode and a virtual electrode, and the first electrode and the virtual electrode are arranged at an interval; the second conducting layer is arranged on the first conducting layer and comprises a grid electrode of the thin film transistor, the grid electrode and the virtual electrode are arranged in a stacked mode, and in the material of the first conducting layer, the molar percentage of tin element is smaller than 1%; wherein the material of the first conductive layer comprises a lanthanide metal oxide, and the molar percentage of the lanthanide element is 1%-5%; and/or the material of the first conductive layer comprises indium metal oxide, and the molar percentage of the indium element is 30%-50%. The problem that etching is not</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB1LCpKrFQoLk0qLilKLEnVUSgoSi1IBDIz8_MUclNLMvJTFEoyUotS89MUEvNSFFIyiwtygDoKEvNSc3gYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSbyzn6GhqbGhkamJmaMxMWoAOBcwUA</recordid><startdate>20221108</startdate><enddate>20221108</enddate><creator>JIANG ZHIXIONG</creator><creator>HUANG JIAHUI</creator><creator>CAI ZHIHUI</creator><creator>GONG CHENG</creator><creator>YU MINGJUE</creator><creator>WANG QIANG</creator><scope>EVB</scope></search><sort><creationdate>20221108</creationdate><title>Array substrate, preparation method thereof and display panel</title><author>JIANG ZHIXIONG ; HUANG JIAHUI ; CAI ZHIHUI ; GONG CHENG ; YU MINGJUE ; WANG QIANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115312546A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JIANG ZHIXIONG</creatorcontrib><creatorcontrib>HUANG JIAHUI</creatorcontrib><creatorcontrib>CAI ZHIHUI</creatorcontrib><creatorcontrib>GONG CHENG</creatorcontrib><creatorcontrib>YU MINGJUE</creatorcontrib><creatorcontrib>WANG QIANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JIANG ZHIXIONG</au><au>HUANG JIAHUI</au><au>CAI ZHIHUI</au><au>GONG CHENG</au><au>YU MINGJUE</au><au>WANG QIANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Array substrate, preparation method thereof and display panel</title><date>2022-11-08</date><risdate>2022</risdate><abstract>The invention provides an array substrate, a preparation method thereof and a display panel, a thin film transistor is arranged in the array substrate, and the array substrate comprises a substrate; the first conducting layer is arranged on the substrate and comprises a first electrode and a virtual electrode, and the first electrode and the virtual electrode are arranged at an interval; the second conducting layer is arranged on the first conducting layer and comprises a grid electrode of the thin film transistor, the grid electrode and the virtual electrode are arranged in a stacked mode, and in the material of the first conducting layer, the molar percentage of tin element is smaller than 1%; wherein the material of the first conductive layer comprises a lanthanide metal oxide, and the molar percentage of the lanthanide element is 1%-5%; and/or the material of the first conductive layer comprises indium metal oxide, and the molar percentage of the indium element is 30%-50%. The problem that etching is not</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN115312546A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Array substrate, preparation method thereof and display panel
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-13T08%3A33%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JIANG%20ZHIXIONG&rft.date=2022-11-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN115312546A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true