Silicon nanowire array type accelerometer based on SOI (Silicon On Insulator) silicon wafer and preparation process of silicon nanowire array type accelerometer
The invention relates to a silicon nanowire array type accelerometer based on an SOI (Silicon On Insulator) silicon wafer and a preparation process of the silicon nanowire array type accelerometer. According to the method, a (111) SOI silicon wafer with 100-type bottom silicon is adopted, and the ac...
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creator | YANG XUN LIU CHAORAN GUO LIKANG ZHENG CHILIN |
description | The invention relates to a silicon nanowire array type accelerometer based on an SOI (Silicon On Insulator) silicon wafer and a preparation process of the silicon nanowire array type accelerometer. According to the method, a (111) SOI silicon wafer with 100-type bottom silicon is adopted, and the accelerometer with high quality and high yield is prepared through anisotropic corrosion, self-limiting thermal oxidation, ion implantation and other processes by utilizing the characteristic that the crystal orientation distribution of a (111) type silicon wafer and the crystal orientation distribution of a (100) type silicon wafer are different. According to the process, the silicon nitride layer on the surface of the silicon wafer is reserved, so that the silicon nanowire is effectively prevented from being broken due to various reasons, and the long-term stability of the silicon nanowire device is greatly improved. Besides, the silicon nitride thin film and the silicon nanowire are adopted to support the mass blo |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN115285933A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN115285933A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN115285933A3</originalsourceid><addsrcrecordid>eNqNjbEKwkAQRNNYiPoPa6eFRQyBWEpQTGOK2If1soGD8-7YPQn5Gz_VK6KtVjMM7zHz5NVoo5WzYNG6QTMBMuMIYfSxKkWG2D0oEMMdhTqIaFNXsPl4tYXKytNgcLwFmdYB-2ig7cAzeWQMOq6enSIRcP0X_Hm7TGY9GqHVlItkfT7dysuOvGtJPCqyFNrymqb5vsgPWXbM_mHeDHlVSg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Silicon nanowire array type accelerometer based on SOI (Silicon On Insulator) silicon wafer and preparation process of silicon nanowire array type accelerometer</title><source>esp@cenet</source><creator>YANG XUN ; LIU CHAORAN ; GUO LIKANG ; ZHENG CHILIN</creator><creatorcontrib>YANG XUN ; LIU CHAORAN ; GUO LIKANG ; ZHENG CHILIN</creatorcontrib><description>The invention relates to a silicon nanowire array type accelerometer based on an SOI (Silicon On Insulator) silicon wafer and a preparation process of the silicon nanowire array type accelerometer. According to the method, a (111) SOI silicon wafer with 100-type bottom silicon is adopted, and the accelerometer with high quality and high yield is prepared through anisotropic corrosion, self-limiting thermal oxidation, ion implantation and other processes by utilizing the characteristic that the crystal orientation distribution of a (111) type silicon wafer and the crystal orientation distribution of a (100) type silicon wafer are different. According to the process, the silicon nitride layer on the surface of the silicon wafer is reserved, so that the silicon nanowire is effectively prevented from being broken due to various reasons, and the long-term stability of the silicon nanowire device is greatly improved. Besides, the silicon nitride thin film and the silicon nanowire are adopted to support the mass blo</description><language>chi ; eng</language><subject>INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT ; MEASURING ; MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION,OR SHOCK ; MICROSTRUCTURAL TECHNOLOGY ; PERFORMING OPERATIONS ; PHYSICS ; PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS ; TESTING ; TRANSPORTING</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221104&DB=EPODOC&CC=CN&NR=115285933A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221104&DB=EPODOC&CC=CN&NR=115285933A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YANG XUN</creatorcontrib><creatorcontrib>LIU CHAORAN</creatorcontrib><creatorcontrib>GUO LIKANG</creatorcontrib><creatorcontrib>ZHENG CHILIN</creatorcontrib><title>Silicon nanowire array type accelerometer based on SOI (Silicon On Insulator) silicon wafer and preparation process of silicon nanowire array type accelerometer</title><description>The invention relates to a silicon nanowire array type accelerometer based on an SOI (Silicon On Insulator) silicon wafer and a preparation process of the silicon nanowire array type accelerometer. According to the method, a (111) SOI silicon wafer with 100-type bottom silicon is adopted, and the accelerometer with high quality and high yield is prepared through anisotropic corrosion, self-limiting thermal oxidation, ion implantation and other processes by utilizing the characteristic that the crystal orientation distribution of a (111) type silicon wafer and the crystal orientation distribution of a (100) type silicon wafer are different. According to the process, the silicon nitride layer on the surface of the silicon wafer is reserved, so that the silicon nanowire is effectively prevented from being broken due to various reasons, and the long-term stability of the silicon nanowire device is greatly improved. Besides, the silicon nitride thin film and the silicon nanowire are adopted to support the mass blo</description><subject>INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT</subject><subject>MEASURING</subject><subject>MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION,OR SHOCK</subject><subject>MICROSTRUCTURAL TECHNOLOGY</subject><subject>PERFORMING OPERATIONS</subject><subject>PHYSICS</subject><subject>PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS</subject><subject>TESTING</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjbEKwkAQRNNYiPoPa6eFRQyBWEpQTGOK2If1soGD8-7YPQn5Gz_VK6KtVjMM7zHz5NVoo5WzYNG6QTMBMuMIYfSxKkWG2D0oEMMdhTqIaFNXsPl4tYXKytNgcLwFmdYB-2ig7cAzeWQMOq6enSIRcP0X_Hm7TGY9GqHVlItkfT7dysuOvGtJPCqyFNrymqb5vsgPWXbM_mHeDHlVSg</recordid><startdate>20221104</startdate><enddate>20221104</enddate><creator>YANG XUN</creator><creator>LIU CHAORAN</creator><creator>GUO LIKANG</creator><creator>ZHENG CHILIN</creator><scope>EVB</scope></search><sort><creationdate>20221104</creationdate><title>Silicon nanowire array type accelerometer based on SOI (Silicon On Insulator) silicon wafer and preparation process of silicon nanowire array type accelerometer</title><author>YANG XUN ; LIU CHAORAN ; GUO LIKANG ; ZHENG CHILIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115285933A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT</topic><topic>MEASURING</topic><topic>MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION,OR SHOCK</topic><topic>MICROSTRUCTURAL TECHNOLOGY</topic><topic>PERFORMING OPERATIONS</topic><topic>PHYSICS</topic><topic>PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS</topic><topic>TESTING</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>YANG XUN</creatorcontrib><creatorcontrib>LIU CHAORAN</creatorcontrib><creatorcontrib>GUO LIKANG</creatorcontrib><creatorcontrib>ZHENG CHILIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YANG XUN</au><au>LIU CHAORAN</au><au>GUO LIKANG</au><au>ZHENG CHILIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Silicon nanowire array type accelerometer based on SOI (Silicon On Insulator) silicon wafer and preparation process of silicon nanowire array type accelerometer</title><date>2022-11-04</date><risdate>2022</risdate><abstract>The invention relates to a silicon nanowire array type accelerometer based on an SOI (Silicon On Insulator) silicon wafer and a preparation process of the silicon nanowire array type accelerometer. According to the method, a (111) SOI silicon wafer with 100-type bottom silicon is adopted, and the accelerometer with high quality and high yield is prepared through anisotropic corrosion, self-limiting thermal oxidation, ion implantation and other processes by utilizing the characteristic that the crystal orientation distribution of a (111) type silicon wafer and the crystal orientation distribution of a (100) type silicon wafer are different. According to the process, the silicon nitride layer on the surface of the silicon wafer is reserved, so that the silicon nanowire is effectively prevented from being broken due to various reasons, and the long-term stability of the silicon nanowire device is greatly improved. Besides, the silicon nitride thin film and the silicon nanowire are adopted to support the mass blo</abstract><oa>free_for_read</oa></addata></record> |
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subjects | INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT MEASURING MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION,OR SHOCK MICROSTRUCTURAL TECHNOLOGY PERFORMING OPERATIONS PHYSICS PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS TESTING TRANSPORTING |
title | Silicon nanowire array type accelerometer based on SOI (Silicon On Insulator) silicon wafer and preparation process of silicon nanowire array type accelerometer |
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