Hardware acceleration method for PQC digital signature algorithm

The invention provides a hardware acceleration method for a PQC digital signature algorithm, and the method comprises the steps: modifying the bit width of an input port or an output port or increasing the number of the ports, so as to improve the parallelism of data transmission; a large number of cycles exist in the source code, the design characteristics of the cycles are analyzed, and optimization is carried out by adopting an optimization mode of cycle expansion or a cycle assembly line; different clock constraints are used to reduce the total time consumption of the overall design runtime. By combining the above optimization analysis and comprehensively considering the latency, the clock frequency and the hardware overhead, a better hardware design scheme is obtained, and the function of improving the PQC hardware calculation speed is achieved. According to the method, different optimizations are implemented according to the characteristics of different cycles, and minimum clock constraints are explored