Cross-clock domain APB bus bridge and method thereof

The invention provides a clock domain crossing APB bus bridge. The APB bus bridge comprises a source clock domain port, a target clock domain port, an FIFO, an APB bus protocol generation circuit and a source clock domain handshake signal generation circuit. According to the method, the FIFO is used for caching write data, and whether the source clock domain handshake signal is pulled up or not is determined according to whether the current transmission is write transmission of write cache enabling and the cache state of the FIFO, that is, whether the source clock domain handshake signal is returned in advance or not is determined, so that it is indicated that the current write transmission is completed to the APB host; therefore, the acceleration of write transmission during write cache enabling is realized. In addition, the invention also provides a cross-clock domain access method executed by the APB bus bridge. 提供了一种跨时钟域的APB总线桥，APB总线桥包括：源时钟域端口、目的时钟域端口、FIFO、APB总线协议产生电路、源时钟域握手信号生成电路。本申请使用FIFO缓存写数据，并根据当前传输是否