Packaging method of stacked chips

Packaging method of stacked chips

The invention discloses a packaging method for stacked chips, and the method comprises the steps: forming a first rewiring layer on a first supporting plate, and fixing a first chip on the first rewiring layer; forming a first plastic package layer at least covering the side surface of the first chi...

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1. Verfasser: CHANG JIANWEI
Format: Patent
Sprache:chi ; eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator CHANG JIANWEI
description The invention discloses a packaging method for stacked chips, and the method comprises the steps: forming a first rewiring layer on a first supporting plate, and fixing a first chip on the first rewiring layer; forming a first plastic package layer at least covering the side surface of the first chip on the first rewiring layer; forming a first conductive piece which penetrates through the first plastic packaging layer and is electrically connected with the first rewiring layer; fixing a second chip on the second support plate, and forming a second plastic package layer at least covering the side surface of the second chip on the second support plate; forming a second conductive piece penetrating through the second plastic packaging layer; the first plastic package layer and the second plastic package layer are connected through a first bonding layer, and the at least one second conductive piece and the at least one first conductive piece are electrically connected in the first bonding layer one by one; and a
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Packaging method of stacked chips
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