Memory array structure and method for determining resistance characteristics of access lines
A memory array structure providing determination of a resistance characteristic of an access line may include: a first block of memory cells; a second block of memory cells; a first current path between a particular access line of the first block of memory cells and a particular access line of the s...
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| creator | XU DAN YU, EDWARD, E XU JUN IWASAKI TOMOMI O TESSARIOL PAOLO |
| description | A memory array structure providing determination of a resistance characteristic of an access line may include: a first block of memory cells; a second block of memory cells; a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells; and an optional second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. A method for determining a resistance characteristic of an access line may include connecting the particular access line of the first block of memory cells to a driver and determining the resistance characteristic in response to a current level through the access line and a voltage level of the access line.
提供存取线的电阻特性的确定的存储器阵列结构可包含：存储器单元的第一块；存储器单元的第二块；第一电流路径，其在存储器单元的所述第一块的特定存取线与存储器单元的所述第二块的特定存取线之间；及任选第二电流路径，其在存储器单元的所述第二块的所述特定存取线与存储器单元的所述第一块的不同存取线之间。用于确定存取线的电阻特性的方法可包含将存储器单元的所述第一块的所述特定存取线连接到驱动器及响应于通过所述存取线的电流电平及所述存取线的电压电平 |
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提供存取线的电阻特性的确定的存储器阵列结构可包含：存储器单元的第一块；存储器单元的第二块；第一电流路径，其在存储器单元的所述第一块的特定存取线与存储器单元的所述第二块的特定存取线之间；及任选第二电流路径，其在存储器单元的所述第二块的所述特定存取线与存储器单元的所述第一块的不同存取线之间。用于确定存取线的电阻特性的方法可包含将存储器单元的所述第一块的所述特定存取线连接到驱动器及响应于通过所述存取线的电流电平及所述存取线的电压电平</description><language>chi ; eng</language><subject>ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220819&DB=EPODOC&CC=CN&NR=114930453A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220819&DB=EPODOC&CC=CN&NR=114930453A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>XU DAN</creatorcontrib><creatorcontrib>YU, EDWARD, E</creatorcontrib><creatorcontrib>XU JUN</creatorcontrib><creatorcontrib>IWASAKI TOMOMI O</creatorcontrib><creatorcontrib>TESSARIOL PAOLO</creatorcontrib><title>Memory array structure and method for determining resistance characteristics of access lines</title><description>A memory array structure providing determination of a resistance characteristic of an access line may include: a first block of memory cells; a second block of memory cells; a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells; and an optional second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. A method for determining a resistance characteristic of an access line may include connecting the particular access line of the first block of memory cells to a driver and determining the resistance characteristic in response to a current level through the access line and a voltage level of the access line.
提供存取线的电阻特性的确定的存储器阵列结构可包含：存储器单元的第一块；存储器单元的第二块；第一电流路径，其在存储器单元的所述第一块的特定存取线与存储器单元的所述第二块的特定存取线之间；及任选第二电流路径，其在存储器单元的所述第二块的所述特定存取线与存储器单元的所述第一块的不同存取线之间。用于确定存取线的电阻特性的方法可包含将存储器单元的所述第一块的所述特定存取线连接到驱动器及响应于通过所述存取线的电流电平及所述存取线的电压电平</description><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNijEKwkAQRdNYiHqH8QCCYWNhKUGx0cpSCMPsj1lIdsPMpsjtTeEBrB6899bF-4Eh6UysyjNZ1knypCCOngbkLnlqk5JHhg4hhvghhQXLHAUkHSvLkhYRxCi1xCIwoz5E2LZYtdwbdj9uiv3t-qrvB4ypgY0siMhN_SzL6uyO1cld3D_PFxaVPIg</recordid><startdate>20220819</startdate><enddate>20220819</enddate><creator>XU DAN</creator><creator>YU, EDWARD, E</creator><creator>XU JUN</creator><creator>IWASAKI TOMOMI O</creator><creator>TESSARIOL PAOLO</creator><scope>EVB</scope></search><sort><creationdate>20220819</creationdate><title>Memory array structure and method for determining resistance characteristics of access lines</title><author>XU DAN ; YU, EDWARD, E ; XU JUN ; IWASAKI TOMOMI O ; TESSARIOL PAOLO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN114930453A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>XU DAN</creatorcontrib><creatorcontrib>YU, EDWARD, E</creatorcontrib><creatorcontrib>XU JUN</creatorcontrib><creatorcontrib>IWASAKI TOMOMI O</creatorcontrib><creatorcontrib>TESSARIOL PAOLO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>XU DAN</au><au>YU, EDWARD, E</au><au>XU JUN</au><au>IWASAKI TOMOMI O</au><au>TESSARIOL PAOLO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory array structure and method for determining resistance characteristics of access lines</title><date>2022-08-19</date><risdate>2022</risdate><abstract>A memory array structure providing determination of a resistance characteristic of an access line may include: a first block of memory cells; a second block of memory cells; a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells; and an optional second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. A method for determining a resistance characteristic of an access line may include connecting the particular access line of the first block of memory cells to a driver and determining the resistance characteristic in response to a current level through the access line and a voltage level of the access line.
提供存取线的电阻特性的确定的存储器阵列结构可包含：存储器单元的第一块；存储器单元的第二块；第一电流路径，其在存储器单元的所述第一块的特定存取线与存储器单元的所述第二块的特定存取线之间；及任选第二电流路径，其在存储器单元的所述第二块的所述特定存取线与存储器单元的所述第一块的不同存取线之间。用于确定存取线的电阻特性的方法可包含将存储器单元的所述第一块的所述特定存取线连接到驱动器及响应于通过所述存取线的电流电平及所述存取线的电压电平</abstract><oa>free_for_read</oa></addata></record> |
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| title | Memory array structure and method for determining resistance characteristics of access lines |
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