Hardware Trojan generation method, system and equipment and medium
The invention provides a hardware Trojan generation method, system and device and a medium, and the method mainly comprises the following steps: carrying out gate-level simulation on a netlist of a target circuit, and obtaining an input waveform of an input node of each standard unit; calling a devi...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | LYU YAOYANG CAI LINLIN ZHENG MINGYUE CHEN WANGYONG |
| description | The invention provides a hardware Trojan generation method, system and device and a medium, and the method mainly comprises the following steps: carrying out gate-level simulation on a netlist of a target circuit, and obtaining an input waveform of an input node of each standard unit; calling a device reliability model, and performing degradation prediction on the device in the target circuit according to the input waveform to obtain a reliability degradation parameter of the device; constructing an aging standard unit time sequence library according to the reliability degradation parameters; performing time sequence simulation according to the aging standard unit time sequence library, and screening to obtain a key path; determining path information and delay information according to the key path, determining a time sequence constraint file, and constructing a hardware Trojan horse circuit according to the time sequence constraint file; the technical scheme of the invention is simple and efficient to impleme |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN114880975A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN114880975A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN114880975A3</originalsourceid><addsrcrecordid>eNrjZHDySCxKKU8sSlUIKcrPSsxTSE_NSy1KLMnMz1PITS3JyE_RUSiuLC5JzVVIzEtRSC0szSzITc0rAfNyU1MyS3N5GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFiMtDIknhnP0NDEwsLA0tzU0djYtQAAD44Mhg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Hardware Trojan generation method, system and equipment and medium</title><source>esp@cenet</source><creator>LYU YAOYANG ; CAI LINLIN ; ZHENG MINGYUE ; CHEN WANGYONG</creator><creatorcontrib>LYU YAOYANG ; CAI LINLIN ; ZHENG MINGYUE ; CHEN WANGYONG</creatorcontrib><description>The invention provides a hardware Trojan generation method, system and device and a medium, and the method mainly comprises the following steps: carrying out gate-level simulation on a netlist of a target circuit, and obtaining an input waveform of an input node of each standard unit; calling a device reliability model, and performing degradation prediction on the device in the target circuit according to the input waveform to obtain a reliability degradation parameter of the device; constructing an aging standard unit time sequence library according to the reliability degradation parameters; performing time sequence simulation according to the aging standard unit time sequence library, and screening to obtain a key path; determining path information and delay information according to the key path, determining a time sequence constraint file, and constructing a hardware Trojan horse circuit according to the time sequence constraint file; the technical scheme of the invention is simple and efficient to impleme</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220809&DB=EPODOC&CC=CN&NR=114880975A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220809&DB=EPODOC&CC=CN&NR=114880975A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LYU YAOYANG</creatorcontrib><creatorcontrib>CAI LINLIN</creatorcontrib><creatorcontrib>ZHENG MINGYUE</creatorcontrib><creatorcontrib>CHEN WANGYONG</creatorcontrib><title>Hardware Trojan generation method, system and equipment and medium</title><description>The invention provides a hardware Trojan generation method, system and device and a medium, and the method mainly comprises the following steps: carrying out gate-level simulation on a netlist of a target circuit, and obtaining an input waveform of an input node of each standard unit; calling a device reliability model, and performing degradation prediction on the device in the target circuit according to the input waveform to obtain a reliability degradation parameter of the device; constructing an aging standard unit time sequence library according to the reliability degradation parameters; performing time sequence simulation according to the aging standard unit time sequence library, and screening to obtain a key path; determining path information and delay information according to the key path, determining a time sequence constraint file, and constructing a hardware Trojan horse circuit according to the time sequence constraint file; the technical scheme of the invention is simple and efficient to impleme</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDySCxKKU8sSlUIKcrPSsxTSE_NSy1KLMnMz1PITS3JyE_RUSiuLC5JzVVIzEtRSC0szSzITc0rAfNyU1MyS3N5GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFiMtDIknhnP0NDEwsLA0tzU0djYtQAAD44Mhg</recordid><startdate>20220809</startdate><enddate>20220809</enddate><creator>LYU YAOYANG</creator><creator>CAI LINLIN</creator><creator>ZHENG MINGYUE</creator><creator>CHEN WANGYONG</creator><scope>EVB</scope></search><sort><creationdate>20220809</creationdate><title>Hardware Trojan generation method, system and equipment and medium</title><author>LYU YAOYANG ; CAI LINLIN ; ZHENG MINGYUE ; CHEN WANGYONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN114880975A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>LYU YAOYANG</creatorcontrib><creatorcontrib>CAI LINLIN</creatorcontrib><creatorcontrib>ZHENG MINGYUE</creatorcontrib><creatorcontrib>CHEN WANGYONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LYU YAOYANG</au><au>CAI LINLIN</au><au>ZHENG MINGYUE</au><au>CHEN WANGYONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Hardware Trojan generation method, system and equipment and medium</title><date>2022-08-09</date><risdate>2022</risdate><abstract>The invention provides a hardware Trojan generation method, system and device and a medium, and the method mainly comprises the following steps: carrying out gate-level simulation on a netlist of a target circuit, and obtaining an input waveform of an input node of each standard unit; calling a device reliability model, and performing degradation prediction on the device in the target circuit according to the input waveform to obtain a reliability degradation parameter of the device; constructing an aging standard unit time sequence library according to the reliability degradation parameters; performing time sequence simulation according to the aging standard unit time sequence library, and screening to obtain a key path; determining path information and delay information according to the key path, determining a time sequence constraint file, and constructing a hardware Trojan horse circuit according to the time sequence constraint file; the technical scheme of the invention is simple and efficient to impleme</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN114880975A |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Hardware Trojan generation method, system and equipment and medium |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T08%3A17%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LYU%20YAOYANG&rft.date=2022-08-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN114880975A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |