Discrete memristor analog circuit and design method thereof
The invention discloses a discrete memristor analog circuit and a design method thereof, and the method comprises the steps: a first anti-phase adder which is used for achieving the iterative accumulation of input charges, and obtaining a first accumulated value; the first phase inverter is used for...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | FU LONGXIANG HE SHAOBO WANG HUIHAI SUN KEHUI |
| description | The invention discloses a discrete memristor analog circuit and a design method thereof, and the method comprises the steps: a first anti-phase adder which is used for achieving the iterative accumulation of input charges, and obtaining a first accumulated value; the first phase inverter is used for restoring the first accumulated value to a positive value to obtain the internal charge qn of the memristor; the input end of the sampling hold circuit is connected with the output end of the first inverter, and the output end is connected with the negative input end of the first inverting adder; the negative input end and the output end of the second phase inverter are connected with the sampling hold circuit, and pulse voltage with opposite phases is input to the sampling hold circuit; the second anti-phase adder is used for realizing the following operation: V (tn) = (alpha-beta qn) i (tn), and alpha and beta are memristor parameters; the positive input end of the voltage follower is connected with an input pow |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN114822641A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN114822641A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN114822641A3</originalsourceid><addsrcrecordid>eNrjZLB2ySxOLkotSVXITc0tyiwuyS9SSMxLzMlPV0jOLEouzSwBclMUUlKLM9PzgGpKMvJTFEoyUotS89N4GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFicmpeakm8s5-hoYmFkZGZiaGjMTFqAMZlL5E</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Discrete memristor analog circuit and design method thereof</title><source>esp@cenet</source><creator>FU LONGXIANG ; HE SHAOBO ; WANG HUIHAI ; SUN KEHUI</creator><creatorcontrib>FU LONGXIANG ; HE SHAOBO ; WANG HUIHAI ; SUN KEHUI</creatorcontrib><description>The invention discloses a discrete memristor analog circuit and a design method thereof, and the method comprises the steps: a first anti-phase adder which is used for achieving the iterative accumulation of input charges, and obtaining a first accumulated value; the first phase inverter is used for restoring the first accumulated value to a positive value to obtain the internal charge qn of the memristor; the input end of the sampling hold circuit is connected with the output end of the first inverter, and the output end is connected with the negative input end of the first inverting adder; the negative input end and the output end of the second phase inverter are connected with the sampling hold circuit, and pulse voltage with opposite phases is input to the sampling hold circuit; the second anti-phase adder is used for realizing the following operation: V (tn) = (alpha-beta qn) i (tn), and alpha and beta are memristor parameters; the positive input end of the voltage follower is connected with an input pow</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220729&DB=EPODOC&CC=CN&NR=114822641A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220729&DB=EPODOC&CC=CN&NR=114822641A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FU LONGXIANG</creatorcontrib><creatorcontrib>HE SHAOBO</creatorcontrib><creatorcontrib>WANG HUIHAI</creatorcontrib><creatorcontrib>SUN KEHUI</creatorcontrib><title>Discrete memristor analog circuit and design method thereof</title><description>The invention discloses a discrete memristor analog circuit and a design method thereof, and the method comprises the steps: a first anti-phase adder which is used for achieving the iterative accumulation of input charges, and obtaining a first accumulated value; the first phase inverter is used for restoring the first accumulated value to a positive value to obtain the internal charge qn of the memristor; the input end of the sampling hold circuit is connected with the output end of the first inverter, and the output end is connected with the negative input end of the first inverting adder; the negative input end and the output end of the second phase inverter are connected with the sampling hold circuit, and pulse voltage with opposite phases is input to the sampling hold circuit; the second anti-phase adder is used for realizing the following operation: V (tn) = (alpha-beta qn) i (tn), and alpha and beta are memristor parameters; the positive input end of the voltage follower is connected with an input pow</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB2ySxOLkotSVXITc0tyiwuyS9SSMxLzMlPV0jOLEouzSwBclMUUlKLM9PzgGpKMvJTFEoyUotS89N4GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFicmpeakm8s5-hoYmFkZGZiaGjMTFqAMZlL5E</recordid><startdate>20220729</startdate><enddate>20220729</enddate><creator>FU LONGXIANG</creator><creator>HE SHAOBO</creator><creator>WANG HUIHAI</creator><creator>SUN KEHUI</creator><scope>EVB</scope></search><sort><creationdate>20220729</creationdate><title>Discrete memristor analog circuit and design method thereof</title><author>FU LONGXIANG ; HE SHAOBO ; WANG HUIHAI ; SUN KEHUI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN114822641A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>FU LONGXIANG</creatorcontrib><creatorcontrib>HE SHAOBO</creatorcontrib><creatorcontrib>WANG HUIHAI</creatorcontrib><creatorcontrib>SUN KEHUI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FU LONGXIANG</au><au>HE SHAOBO</au><au>WANG HUIHAI</au><au>SUN KEHUI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Discrete memristor analog circuit and design method thereof</title><date>2022-07-29</date><risdate>2022</risdate><abstract>The invention discloses a discrete memristor analog circuit and a design method thereof, and the method comprises the steps: a first anti-phase adder which is used for achieving the iterative accumulation of input charges, and obtaining a first accumulated value; the first phase inverter is used for restoring the first accumulated value to a positive value to obtain the internal charge qn of the memristor; the input end of the sampling hold circuit is connected with the output end of the first inverter, and the output end is connected with the negative input end of the first inverting adder; the negative input end and the output end of the second phase inverter are connected with the sampling hold circuit, and pulse voltage with opposite phases is input to the sampling hold circuit; the second anti-phase adder is used for realizing the following operation: V (tn) = (alpha-beta qn) i (tn), and alpha and beta are memristor parameters; the positive input end of the voltage follower is connected with an input pow</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN114822641A |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Discrete memristor analog circuit and design method thereof |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T10%3A34%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=FU%20LONGXIANG&rft.date=2022-07-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN114822641A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |