Molded semiconductor package with high voltage isolation
A molded semiconductor package includes a semiconductor die attached to a substrate, the semiconductor die including a bond pad at a first side of the semiconductor die facing away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a portion of th...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | REYNOSO DANIEL I SCHREDL JUERGEN RUAN YUPING AQUITAN, ERIC, B YANG WENYI |
| description | A molded semiconductor package includes a semiconductor die attached to a substrate, the semiconductor die including a bond pad at a first side of the semiconductor die facing away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a portion of the bond pad exposed through an opening in the insulating layer; a molding compound surrounding the semiconductor die; and an electrically insulating material filling the opening in the insulating layer and sealing the portion of the bond pad exposed through the opening in the insulating layer. The electrically insulating material separates the molding compound from the portion of the bond pad exposed through the opening in the insulating layer. A breakdown voltage of the electrically insulating material is greater than a breakdown voltage of the molding compound.
一种模制半导体封装包括：附接到衬底的半导体管芯，所述半导体管芯包括在所述半导体管芯的背离所述衬底的第一侧处的接合焊盘和覆盖所述第一侧的绝缘层；电导体，其附接到所述接合焊盘的通过所述绝缘层中的开口暴露的部分；包围所述半导体管芯的模制化合物；以及电绝缘材料，其填充所述绝缘层中的所述开口并且密封所述接合焊盘的通过所 |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN114597190A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN114597190A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN114597190A3</originalsourceid><addsrcrecordid>eNrjZLDwzc9JSU1RKE7NzUzOz0spTS7JL1IoSEzOTkxPVSjPLMlQyMhMz1Aoy88pAYlkFufnJJZk5ufxMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjUYqAJqXmpJfHOfoaGJqaW5oaWBo7GxKgBAC8uLqk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Molded semiconductor package with high voltage isolation</title><source>esp@cenet</source><creator>REYNOSO DANIEL I ; SCHREDL JUERGEN ; RUAN YUPING ; AQUITAN, ERIC, B ; YANG WENYI</creator><creatorcontrib>REYNOSO DANIEL I ; SCHREDL JUERGEN ; RUAN YUPING ; AQUITAN, ERIC, B ; YANG WENYI</creatorcontrib><description>A molded semiconductor package includes a semiconductor die attached to a substrate, the semiconductor die including a bond pad at a first side of the semiconductor die facing away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a portion of the bond pad exposed through an opening in the insulating layer; a molding compound surrounding the semiconductor die; and an electrically insulating material filling the opening in the insulating layer and sealing the portion of the bond pad exposed through the opening in the insulating layer. The electrically insulating material separates the molding compound from the portion of the bond pad exposed through the opening in the insulating layer. A breakdown voltage of the electrically insulating material is greater than a breakdown voltage of the molding compound.
一种模制半导体封装包括：附接到衬底的半导体管芯，所述半导体管芯包括在所述半导体管芯的背离所述衬底的第一侧处的接合焊盘和覆盖所述第一侧的绝缘层；电导体，其附接到所述接合焊盘的通过所述绝缘层中的开口暴露的部分；包围所述半导体管芯的模制化合物；以及电绝缘材料，其填充所述绝缘层中的所述开口并且密封所述接合焊盘的通过所</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220607&DB=EPODOC&CC=CN&NR=114597190A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220607&DB=EPODOC&CC=CN&NR=114597190A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>REYNOSO DANIEL I</creatorcontrib><creatorcontrib>SCHREDL JUERGEN</creatorcontrib><creatorcontrib>RUAN YUPING</creatorcontrib><creatorcontrib>AQUITAN, ERIC, B</creatorcontrib><creatorcontrib>YANG WENYI</creatorcontrib><title>Molded semiconductor package with high voltage isolation</title><description>A molded semiconductor package includes a semiconductor die attached to a substrate, the semiconductor die including a bond pad at a first side of the semiconductor die facing away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a portion of the bond pad exposed through an opening in the insulating layer; a molding compound surrounding the semiconductor die; and an electrically insulating material filling the opening in the insulating layer and sealing the portion of the bond pad exposed through the opening in the insulating layer. The electrically insulating material separates the molding compound from the portion of the bond pad exposed through the opening in the insulating layer. A breakdown voltage of the electrically insulating material is greater than a breakdown voltage of the molding compound.
一种模制半导体封装包括：附接到衬底的半导体管芯，所述半导体管芯包括在所述半导体管芯的背离所述衬底的第一侧处的接合焊盘和覆盖所述第一侧的绝缘层；电导体，其附接到所述接合焊盘的通过所述绝缘层中的开口暴露的部分；包围所述半导体管芯的模制化合物；以及电绝缘材料，其填充所述绝缘层中的所述开口并且密封所述接合焊盘的通过所</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDwzc9JSU1RKE7NzUzOz0spTS7JL1IoSEzOTkxPVSjPLMlQyMhMz1Aoy88pAYlkFufnJJZk5ufxMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjUYqAJqXmpJfHOfoaGJqaW5oaWBo7GxKgBAC8uLqk</recordid><startdate>20220607</startdate><enddate>20220607</enddate><creator>REYNOSO DANIEL I</creator><creator>SCHREDL JUERGEN</creator><creator>RUAN YUPING</creator><creator>AQUITAN, ERIC, B</creator><creator>YANG WENYI</creator><scope>EVB</scope></search><sort><creationdate>20220607</creationdate><title>Molded semiconductor package with high voltage isolation</title><author>REYNOSO DANIEL I ; SCHREDL JUERGEN ; RUAN YUPING ; AQUITAN, ERIC, B ; YANG WENYI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN114597190A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>REYNOSO DANIEL I</creatorcontrib><creatorcontrib>SCHREDL JUERGEN</creatorcontrib><creatorcontrib>RUAN YUPING</creatorcontrib><creatorcontrib>AQUITAN, ERIC, B</creatorcontrib><creatorcontrib>YANG WENYI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>REYNOSO DANIEL I</au><au>SCHREDL JUERGEN</au><au>RUAN YUPING</au><au>AQUITAN, ERIC, B</au><au>YANG WENYI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Molded semiconductor package with high voltage isolation</title><date>2022-06-07</date><risdate>2022</risdate><abstract>A molded semiconductor package includes a semiconductor die attached to a substrate, the semiconductor die including a bond pad at a first side of the semiconductor die facing away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a portion of the bond pad exposed through an opening in the insulating layer; a molding compound surrounding the semiconductor die; and an electrically insulating material filling the opening in the insulating layer and sealing the portion of the bond pad exposed through the opening in the insulating layer. The electrically insulating material separates the molding compound from the portion of the bond pad exposed through the opening in the insulating layer. A breakdown voltage of the electrically insulating material is greater than a breakdown voltage of the molding compound.
一种模制半导体封装包括：附接到衬底的半导体管芯，所述半导体管芯包括在所述半导体管芯的背离所述衬底的第一侧处的接合焊盘和覆盖所述第一侧的绝缘层；电导体，其附接到所述接合焊盘的通过所述绝缘层中的开口暴露的部分；包围所述半导体管芯的模制化合物；以及电绝缘材料，其填充所述绝缘层中的所述开口并且密封所述接合焊盘的通过所</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN114597190A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Molded semiconductor package with high voltage isolation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T23%3A45%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=REYNOSO%20DANIEL%20I&rft.date=2022-06-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN114597190A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |