Hardware accelerator

A hardware accelerator includes: a first memory; a source address generating unit coupled to the first memory; a data collection unit coupled to the first memory; a first data queue coupled to the data collection unit; a data dispersion unit coupled to the first data queue; a target address generation unit coupled to the data dispersion unit; the address queue is coupled to the target address generating unit; a second data queue coupled to the data dispersion unit; and a second memory coupled to the second data queue. The hardware accelerator can perform one or any combination of tensor movement, tensor remodeling shape and tensor exchange sequence to achieve tensor depth-to-space arrangement or tensor space-to-depth arrangement. 一种硬件加速器，其包括：一第一存储器；一来源地址产生单元，耦接至该第一存储器；一数据收集单元，耦接至该第一存储器；一第一数据队列，耦接至该数据收集单元；一数据分散单元，耦接至该第一数据队列；一目标地址产生单元，耦接至该数据分散单元；一地址队列，耦接至该目标位址产生单元；一第二数据队列，耦接至该数据分散单元；以及一第二存储器，耦接至该第二数据队列。该硬件加速器可进行张量移动、张量重塑形状与张量对换顺序的其中之一或者任意组合，以达到张量深度到空间排列或张量空间到深度排列。