Three-dimensional integrated wafer, test method thereof and three-dimensional integrated chip

The invention provides a three-dimensional integrated wafer and a test method thereof, and a three-dimensional integrated chip, and the three-dimensional integrated wafer comprises a wafer assembly which is composed of a plurality of wafer layers, and the wafer layers are stacked and are connected t...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ZHU XIAOWEI, GAO XUDONG, MA BIN, CHAI JINGRUI, MA LE, GUO XING, YIN PENG
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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