Three-dimensional integrated wafer, test method thereof and three-dimensional integrated chip

The invention provides a three-dimensional integrated wafer and a test method thereof, and a three-dimensional integrated chip, and the three-dimensional integrated wafer comprises a wafer assembly which is composed of a plurality of wafer layers, and the wafer layers are stacked and are connected through a connection structure. The wafer assembly comprises a plurality of chip units, the periphery of each chip unit is provided with the detection loop, and the detection loop is configured to detect the connection condition of the plurality of wafer layers in each chip unit. The structure can effectively monitor the layering problem of the wafer in the chip, and improves the yield of the chip. 本发明提供一种三维集成晶圆及其测试方法、三维集成芯片，三维集成晶圆包括：由多个晶圆层组成的晶圆组件，晶圆层层叠设置且通过连接结构连接；所述晶圆组件包括多个芯片单元，每一所述芯片单元的周围设置有所述检测环路，所述检测环路被配置为检测每一所述芯片单元中多个所述晶圆层的连接情况。该结构能够有效的监控芯片中晶圆的分层问题，提高了芯片的成品率。