Intelligent substation merging unit SV sending control method and device
The invention discloses an intelligent substation merging unit SV sending control method and device. The method comprises the following steps: obtaining the latest sending time mark of an FPGA; calculating a time scale difference value of the FPGA and the CPU according to the pre-sent time scale of...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , , , , , , , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | PAN SONGJIE YUE XIAOYANG WANG XIAOFENG LI JIE ZHU JIANBIN YANG KAI YU GAOWANG NI YUNLING HAO WEI NI CHUANKUN YANG PEIDI LI CHAO XU YUNLONG YAN ZHIHUI ZHENG YEBING ZHANG RONGLIANG LI BAOWEI LING TELI ZHOU DONGJIE ZHENG TUOFU ZHOU SHUIBIN LI LEI |
| description | The invention discloses an intelligent substation merging unit SV sending control method and device. The method comprises the following steps: obtaining the latest sending time mark of an FPGA; calculating a time scale difference value of the FPGA and the CPU according to the pre-sent time scale of the CPU; judging whether the time scale difference value is continuously greater than a first preset time length for a first preset number of times; if so, judging that the FPGA sends SV abnormally, and carrying out reset operation on the FPGA; and if not, controlling the FPGA to send the SV packet. Whether SV sending is normal or not is determined by judging the time scale difference value of the CPU and the FPGA in the merging unit, and the problem that SV sending is interrupted due to running-away of an SV sending logic state machine of the FPGA is solved; the sending reliability of the merging unit SV is improved, the reliability of the data source of the intelligent substation is enhanced, and safe and stable |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN114039414A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN114039414A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN114039414A3</originalsourceid><addsrcrecordid>eNrjZPDwzCtJzcnJTE_NK1EoLk0qLkksyczPU8hNLUrPzEtXKM3LLFEIDlMoTs1LAfGT8_NKivJzgPIlGfkpCol5KQopqWWZyak8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61uCAxOTUvtSTe2c_Q0MTA2NLE0MTRmBg1AMo_NG8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Intelligent substation merging unit SV sending control method and device</title><source>esp@cenet</source><creator>PAN SONGJIE ; YUE XIAOYANG ; WANG XIAOFENG ; LI JIE ; ZHU JIANBIN ; YANG KAI ; YU GAOWANG ; NI YUNLING ; HAO WEI ; NI CHUANKUN ; YANG PEIDI ; LI CHAO ; XU YUNLONG ; YAN ZHIHUI ; ZHENG YEBING ; ZHANG RONGLIANG ; LI BAOWEI ; LING TELI ; ZHOU DONGJIE ; ZHENG TUOFU ; ZHOU SHUIBIN ; LI LEI</creator><creatorcontrib>PAN SONGJIE ; YUE XIAOYANG ; WANG XIAOFENG ; LI JIE ; ZHU JIANBIN ; YANG KAI ; YU GAOWANG ; NI YUNLING ; HAO WEI ; NI CHUANKUN ; YANG PEIDI ; LI CHAO ; XU YUNLONG ; YAN ZHIHUI ; ZHENG YEBING ; ZHANG RONGLIANG ; LI BAOWEI ; LING TELI ; ZHOU DONGJIE ; ZHENG TUOFU ; ZHOU SHUIBIN ; LI LEI</creatorcontrib><description>The invention discloses an intelligent substation merging unit SV sending control method and device. The method comprises the following steps: obtaining the latest sending time mark of an FPGA; calculating a time scale difference value of the FPGA and the CPU according to the pre-sent time scale of the CPU; judging whether the time scale difference value is continuously greater than a first preset time length for a first preset number of times; if so, judging that the FPGA sends SV abnormally, and carrying out reset operation on the FPGA; and if not, controlling the FPGA to send the SV packet. Whether SV sending is normal or not is determined by judging the time scale difference value of the CPU and the FPGA in the merging unit, and the problem that SV sending is interrupted due to running-away of an SV sending logic state machine of the FPGA is solved; the sending reliability of the merging unit SV is improved, the reliability of the data source of the intelligent substation is enhanced, and safe and stable</description><language>chi ; eng</language><subject>CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTINGELECTRIC POWER ; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ; ELECTRICITY ; GENERATION ; SYSTEMS FOR STORING ELECTRIC ENERGY</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220211&DB=EPODOC&CC=CN&NR=114039414A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220211&DB=EPODOC&CC=CN&NR=114039414A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PAN SONGJIE</creatorcontrib><creatorcontrib>YUE XIAOYANG</creatorcontrib><creatorcontrib>WANG XIAOFENG</creatorcontrib><creatorcontrib>LI JIE</creatorcontrib><creatorcontrib>ZHU JIANBIN</creatorcontrib><creatorcontrib>YANG KAI</creatorcontrib><creatorcontrib>YU GAOWANG</creatorcontrib><creatorcontrib>NI YUNLING</creatorcontrib><creatorcontrib>HAO WEI</creatorcontrib><creatorcontrib>NI CHUANKUN</creatorcontrib><creatorcontrib>YANG PEIDI</creatorcontrib><creatorcontrib>LI CHAO</creatorcontrib><creatorcontrib>XU YUNLONG</creatorcontrib><creatorcontrib>YAN ZHIHUI</creatorcontrib><creatorcontrib>ZHENG YEBING</creatorcontrib><creatorcontrib>ZHANG RONGLIANG</creatorcontrib><creatorcontrib>LI BAOWEI</creatorcontrib><creatorcontrib>LING TELI</creatorcontrib><creatorcontrib>ZHOU DONGJIE</creatorcontrib><creatorcontrib>ZHENG TUOFU</creatorcontrib><creatorcontrib>ZHOU SHUIBIN</creatorcontrib><creatorcontrib>LI LEI</creatorcontrib><title>Intelligent substation merging unit SV sending control method and device</title><description>The invention discloses an intelligent substation merging unit SV sending control method and device. The method comprises the following steps: obtaining the latest sending time mark of an FPGA; calculating a time scale difference value of the FPGA and the CPU according to the pre-sent time scale of the CPU; judging whether the time scale difference value is continuously greater than a first preset time length for a first preset number of times; if so, judging that the FPGA sends SV abnormally, and carrying out reset operation on the FPGA; and if not, controlling the FPGA to send the SV packet. Whether SV sending is normal or not is determined by judging the time scale difference value of the CPU and the FPGA in the merging unit, and the problem that SV sending is interrupted due to running-away of an SV sending logic state machine of the FPGA is solved; the sending reliability of the merging unit SV is improved, the reliability of the data source of the intelligent substation is enhanced, and safe and stable</description><subject>CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTINGELECTRIC POWER</subject><subject>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</subject><subject>ELECTRICITY</subject><subject>GENERATION</subject><subject>SYSTEMS FOR STORING ELECTRIC ENERGY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPDwzCtJzcnJTE_NK1EoLk0qLkksyczPU8hNLUrPzEtXKM3LLFEIDlMoTs1LAfGT8_NKivJzgPIlGfkpCol5KQopqWWZyak8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61uCAxOTUvtSTe2c_Q0MTA2NLE0MTRmBg1AMo_NG8</recordid><startdate>20220211</startdate><enddate>20220211</enddate><creator>PAN SONGJIE</creator><creator>YUE XIAOYANG</creator><creator>WANG XIAOFENG</creator><creator>LI JIE</creator><creator>ZHU JIANBIN</creator><creator>YANG KAI</creator><creator>YU GAOWANG</creator><creator>NI YUNLING</creator><creator>HAO WEI</creator><creator>NI CHUANKUN</creator><creator>YANG PEIDI</creator><creator>LI CHAO</creator><creator>XU YUNLONG</creator><creator>YAN ZHIHUI</creator><creator>ZHENG YEBING</creator><creator>ZHANG RONGLIANG</creator><creator>LI BAOWEI</creator><creator>LING TELI</creator><creator>ZHOU DONGJIE</creator><creator>ZHENG TUOFU</creator><creator>ZHOU SHUIBIN</creator><creator>LI LEI</creator><scope>EVB</scope></search><sort><creationdate>20220211</creationdate><title>Intelligent substation merging unit SV sending control method and device</title><author>PAN SONGJIE ; YUE XIAOYANG ; WANG XIAOFENG ; LI JIE ; ZHU JIANBIN ; YANG KAI ; YU GAOWANG ; NI YUNLING ; HAO WEI ; NI CHUANKUN ; YANG PEIDI ; LI CHAO ; XU YUNLONG ; YAN ZHIHUI ; ZHENG YEBING ; ZHANG RONGLIANG ; LI BAOWEI ; LING TELI ; ZHOU DONGJIE ; ZHENG TUOFU ; ZHOU SHUIBIN ; LI LEI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN114039414A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTINGELECTRIC POWER</topic><topic>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</topic><topic>ELECTRICITY</topic><topic>GENERATION</topic><topic>SYSTEMS FOR STORING ELECTRIC ENERGY</topic><toplevel>online_resources</toplevel><creatorcontrib>PAN SONGJIE</creatorcontrib><creatorcontrib>YUE XIAOYANG</creatorcontrib><creatorcontrib>WANG XIAOFENG</creatorcontrib><creatorcontrib>LI JIE</creatorcontrib><creatorcontrib>ZHU JIANBIN</creatorcontrib><creatorcontrib>YANG KAI</creatorcontrib><creatorcontrib>YU GAOWANG</creatorcontrib><creatorcontrib>NI YUNLING</creatorcontrib><creatorcontrib>HAO WEI</creatorcontrib><creatorcontrib>NI CHUANKUN</creatorcontrib><creatorcontrib>YANG PEIDI</creatorcontrib><creatorcontrib>LI CHAO</creatorcontrib><creatorcontrib>XU YUNLONG</creatorcontrib><creatorcontrib>YAN ZHIHUI</creatorcontrib><creatorcontrib>ZHENG YEBING</creatorcontrib><creatorcontrib>ZHANG RONGLIANG</creatorcontrib><creatorcontrib>LI BAOWEI</creatorcontrib><creatorcontrib>LING TELI</creatorcontrib><creatorcontrib>ZHOU DONGJIE</creatorcontrib><creatorcontrib>ZHENG TUOFU</creatorcontrib><creatorcontrib>ZHOU SHUIBIN</creatorcontrib><creatorcontrib>LI LEI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PAN SONGJIE</au><au>YUE XIAOYANG</au><au>WANG XIAOFENG</au><au>LI JIE</au><au>ZHU JIANBIN</au><au>YANG KAI</au><au>YU GAOWANG</au><au>NI YUNLING</au><au>HAO WEI</au><au>NI CHUANKUN</au><au>YANG PEIDI</au><au>LI CHAO</au><au>XU YUNLONG</au><au>YAN ZHIHUI</au><au>ZHENG YEBING</au><au>ZHANG RONGLIANG</au><au>LI BAOWEI</au><au>LING TELI</au><au>ZHOU DONGJIE</au><au>ZHENG TUOFU</au><au>ZHOU SHUIBIN</au><au>LI LEI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Intelligent substation merging unit SV sending control method and device</title><date>2022-02-11</date><risdate>2022</risdate><abstract>The invention discloses an intelligent substation merging unit SV sending control method and device. The method comprises the following steps: obtaining the latest sending time mark of an FPGA; calculating a time scale difference value of the FPGA and the CPU according to the pre-sent time scale of the CPU; judging whether the time scale difference value is continuously greater than a first preset time length for a first preset number of times; if so, judging that the FPGA sends SV abnormally, and carrying out reset operation on the FPGA; and if not, controlling the FPGA to send the SV packet. Whether SV sending is normal or not is determined by judging the time scale difference value of the CPU and the FPGA in the merging unit, and the problem that SV sending is interrupted due to running-away of an SV sending logic state machine of the FPGA is solved; the sending reliability of the merging unit SV is improved, the reliability of the data source of the intelligent substation is enhanced, and safe and stable</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN114039414A |
| source | esp@cenet |
| subjects | CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTINGELECTRIC POWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY GENERATION SYSTEMS FOR STORING ELECTRIC ENERGY |
| title | Intelligent substation merging unit SV sending control method and device |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T23%3A37%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PAN%20SONGJIE&rft.date=2022-02-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN114039414A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |